circuit analysisoperational-amplifier
We are supposed to find \$R\$ such that \$I_S=0\$ and then find the maximum \$V_{SRC}\$ for operation in the linear region. I tried to use KCL at the nodes but it didn't work out eventually since I got a value of R that is negative. And for the second part of the question how does one determine the maximum possible value in the linear range: I am not sure how to go about this. I would appreciate any help.
KCL at the center node gives:
$$ \frac{-V_x-50}{10} + 5 + 0.1V_x + \frac{-V_x}{20} = 0 $$
Which is only an equation of \$V_x\$ and can be immediately solved to get \$V_x = 0\$.
KCL at the top node (with voltage \$V_T\$):
$$ \frac{V_T - 50}{20} - 5 + I_Y = 0 $$
Ohm's law on the 25 ohm resistor gives \$ I_Y = \frac{V_T - 5I_Y}{25} \implies V_T = 30I_Y\$. Using this in the preceeding equation gives:
$$ \frac{30I_Y - 50}{20} - 5 + I_Y = 0 \implies I_Y = 3 \text{A}$$
So, along with your own answer and Alfred Centauri's answer, we can conclude that your book's answer of \$V_X = 70 V\$ is incorrect.
I don't know how to proceed with this question or where to start.
If there is (net) negative feedback, then you proceed by setting the voltage across the op-amp input terminals equal to zero:
$$v_+ = v_-$$
Note that with zero volts across the input terminals, the 2k resistor in parallel with the current source is irrelevant; there is zero volts across it so there is zero current through it. You may remove it from the circuit without changing the solution.
This should get you started.
@AlfredCentauri I still don't see the bottom loop, do you mean the loop v+ connected to VB then connected to the voltage source and then the resistor and finally VA. Is that considered a loop even with the op-amp? And when I do I still don't get your equation.
simulate this circuit – Schematic created using CircuitLab
This is the bottom-most loop and KVL clock-wise 'round the loop starting with the voltage across the 1k resistor is:
$$i_1 \cdot 1k\Omega -2V + V_B - V_A = 0 $$
rearranging yields
$$V_B = V_A - i_1 \cdot 1k\Omega + 2V$$
If the presence of the voltage source above is puzzling, recall that the output of the ideal op-amp is an ideal (controlled) voltage voltage source referenced to ground which I've shown explicitly here.
Best Answer
Step by step:
The current, from left to right, through \$R\$ is
$$I_R = \frac{V_{SRC} - V_{O2}}{R} $$
The current, from left to right, through the left-most 10k resistor is
$$I_{10k} = \frac{V_{SRC}}{10k\Omega} $$
KCL at the input node yields
$$I_S = I_R + I_{10k}$$
Using the well-known inverting op-amp gain formula, the two op-amp cascade has a gain of
$$\frac{V_{O2}}{V_{SRC}} = (-\frac{40k}{10k}) \cdot (-\frac{20k}{10k}) = 8 $$
Now, set \$I_S = 0\$ and solve.
A rewarding exercise is to solve for the input resistance seen by the input voltage source:
$$R_{IN} = \frac{V_{SRC}}{I_S} = \frac{V_{SRC}}{I_R + I_{10k}} = \frac{1}{\frac{1}{10k\Omega} - \frac{7}{R}}$$
Note that the input resistance is positive for \$R > 70k\Omega\$, is negative for \$R < 70k\Omega\$ (the circuit supplies power to the voltage source), and is 'infinite' (open circuit) for \$R = 70k\Omega\$