Electronic – SPI chip select –> data + clock delay tolerance

spitiming

I know this likely depends on the specific chips and devices being used, but I'm just looking for estimate ballpark numbers.

I'm considering using the spi protocol for a project, and I can't seem to find any good timing diagrams, on the time tolerance from the assertion of the chip select till data must be pushed on the data line.

I'd love to be shown such diagrams for different devices, and what seems to be 'standard values', assuming that's a thing.

This is a learning project, electronics is not my main field.

Best Answer

It goes the opposite way: the delay must be no shorter than a certain value, usually a couple hundred ns. Moreover, it's the delay between assertion of CS and the first edge of the clock signal. It has nothing to do with the data line at all.

Note that this "delay" can always be infinite. If you have only one slave device, you can typically keep CS permanently asserted, unless there's no other way to recover the inevitable clock slip than cycling CS (think of interference).

The question is, then: are you trying to design an SPI slave, an SPI master, or a system that has both? If you control the master, then you can always guarantee sufficient delay between CS and SCLK - it's a matter of programming it right.


Since your intention is to switch the CS signals manually, you must debounce them. A simple push to toggle implementation is shown below:

schematic

simulate this circuit – Schematic created using CircuitLab

You'd need a way to reset all other chip selects when any one of them is activated.