Electronic – Split digital ground planes

Some time ago, I answered a similar question here.

The first sentence, which is an echo of commenters here is:

Unless there is a compelling reason otherwise, I use the same ground everywhere.

The Maxim application note is targeted at mixed signal integrated circuits, where, unless you take precautions, the digital and analogue currents will overlap, and the usual method of managing this is to tie the effective digital and analogue grounds is at a single point (usually beneath the device).

Understanding how the currents move in the plane(s) is the key to good signal integrity, and the general rule of putting the sensitive circuitry furthest from power and the noisy stuff close to it is a good rule of thumb, but every design needs to be analysed for clean power and grounds (the return path which is the 50% of the power that does not seem to appear in a schematic but is just as important, of course).

[Update]

Under very limited circumstances, a split plane may be appropriate. There is a trade-off of effort vs. return on that effort. In an ordinary mixed mode system, I would not split the planes.

The example was a specific design that had very high eddy currents on the LEDs where it was easier (and appropriate) to split the planes to prevent those eddy currents from inducing into the other LEDs. The grounds were tied together at the primary power inlet to the board.

I think my primary point on where things are placed is that sensitive devices should not have return currents from other devices under them. In a system with high speed logic and ADCs, I would put the ADCs at the end of the power path so that the digital returns cannot interfere with the measurements.

Perhaps I had not made that as clear as it could have been.

HTH

You got to think in terms of shared impedance (not resistance, really impedance).

Consider the parts of the circuit that use GND as a 0V reference for sensitive analog purposes. Obviously you want each of these "0V references" to be at the same "0V" potential. However current running through the GND plane will introduce an extra error voltage on top of each chip's "0V".

Now draw a schematic of your GND, with the currents running through it.

If you do not split the plane, but you have high currents running through it, because you put the power input connector on the left side, the power output connector on the right side, and the super sensitive analog bits in the middle, then you might have a problem due to high current flowing in GND and creating a voltage gradient.

Depending on frequency, consider impedance (ie, inductance, not just resistance).

Now, there are several solutions to this.

• You could put your power connectors in more reasonable places (ie, power input next to power output) so the high currents do not travel in your GND plane. This applies to all current loops which carry large, noisy, or high di/dt currents, like the internal loops of a DCDC, or the loops between it and its load (say, a cpu) or even the ground path between a decoupling cap and the chip it decouples.

Make sure you know where these loops are! Order them by troublesomeness (roughly "area * di/dt" for AC or "area*I" for DC). Placement is essential. A good placement with tight current loops makes layout much less of a headache.

• You could use differential amplifiers and ADCs which ignore common mode noise.

This is mandatory if the voltage to sense sits on a high-side current shunt. Now let's say you use a current sense amp for example. Dont forget whatever voltage is on its "output reference" pin (often mislabeled "GND") is directly added to the output... so dont stick the sense amp between two MOSFETs with its "GND" pin in the middle of the "motor current return" path...

• You could also split the plane, but then you need to decide where you gonna split it. And (this is where things get nasty) where you link your two grounds together at DC (or at high frequencies if you use isolators...

Let's name your two grounds AGND and PGND (analog and power). Some say to split, and join AGND/PGND or AGND/DGND under the ADC. This means any current that runs between AGND and PGND has to flow in the ground link under the ADC now, which is the worst possible place.

A solution that makes lots of sense is the "hidden split". Placement is essential. For example you put the power/noisy stuff on the right, and the sensitive stuff on the left. You place your decoupling caps so the supply currents loops running through GND are short and well placed. Then, since your board has two well defined zones, you can narrow down the width of ground plane connecting them, to ensure high currents do not run in the sensitive bits' ground.

It's very visual and difficult to explain, and placing your connectors properly is essential.

These tutorials are good: https://learnemc.com/emc-tutorials