I'm trying to design a State Machine that acts as a synchronous lock. There is only 1 input (X) and one output (Lock= 0, Unlock = 5v). The machine will only unlock if the following order is put in: 0* 1* 1* 0* 1* 1* 0. (An asterisk means I then push the clock button. So it should switch to unlocked after just changing the input from 1 to 0) Only this combination should unlock it. A reset button should also be included.
My professor gave us the State Table and Diagram for the project. I have tried to implement it using JK and D flip flops, to no avail.
A classmate said to try using a 4×16 Decoder, with active low output, to do the project. He said to NAND the 0 outputs, and use D Flip Flops.So I put a NAND to the zeroes of each Next State, and connect it to the D Flip Flops, right?
Also, how then do I get my output? Do I AND the 3 D Outputs (Qa Qb and Qc) as well as my X Input?
Additional information: We use TTL (0 and 5v only) and I have to design this out on a hardware trainer.
Best Answer
What you are designing is basically a sequence detector.What you need to do is set up 8 states, each of which representing the current state the circuit might be in, and the draw a state transition table ( table showing how every current state maps to a next state ), then extract the sequential circuit that will be needed to implement the circuit.
A document explaining in detail how to design such a circuit can be seen HERE.