Electronic – std_logic or std_ulogic

vhdl

It seems that the world has decided that std_logic (and std_logic_vector) are the default way of representing bits in VHDL. The alternative would be std_ulogic, which is not resolved.

This surprises me because usually, you're not describing a bus, so you do you don't want multiple drivers and you don't need to resolve a signal. The advantage of std_ulogic would be that the compiler warns you early on if you have multiple drivers.

Question: is this just a cultural / historical thing, or are there still technical reasons to use std_logic?

Best Answer

Std_logic is a subtype of std_ulogic and has exactly one extra property: it's resolved if there are multiple drivers.

Regardless of common practice, std_ulogic is the correct type to use for non-resolved signals that need 9-valued logic. (Often, using "bit" is even more correct -- for instance, on some FPGA architectures that do not have any such thing as an 'X' or a 'U').

Basically, the best thing to do is use the correct type for the job. Often bad practices get propagated by people just parroting the style that they see others use, do without understanding why.

Related Solutions

Electronic – When to use STD_LOGIC over BIT in VHDL

Bit is a predefined type and only can only have the value 0 or 1. The Bit type is an idealized value.

type Bit is ('0', '1');

std_logic is part of the std_logic_1164 package and provides more realistic modeling of signals within a digital system. It is capable of having nine different values. Typically within your code you will only use 0, 1, and Z (High-Z). But U (Uninitialized) and X (Unknown) are also very useful when modeling the system in a testbench.

    -------------------------------------------------------------------    
    -- logic state system  (unresolved)
    -------------------------------------------------------------------    
    TYPE std_ulogic IS ( 'U',  -- Uninitialized
                         'X',  -- Forcing  Unknown
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance   
                         'W',  -- Weak     Unknown
                         'L',  -- Weak     0       
                         'H',  -- Weak     1       
                         '-'   -- Don't care
                       );

--    attribute ENUM_ENCODING of std_ulogic : type is "U D 0 1 Z D 0 1 D";

    -------------------------------------------------------------------    
    -- *** industry standard logic type ***
    -------------------------------------------------------------------    
    SUBTYPE std_logic IS resolved std_ulogic;

The std_logic_1164 package also provides conversion functions to convert std_logic to Bit.

Target type std.standard.bit in variable assignment is different from std_logic_1164.std_ulogic

The type 'bit' is rarely used. Let's call this academic code :-) Change your 'bit' signals and variables to the type 'std_logic' should/could fix your problem. (I did not test it with your code)

BTW: try to avoid using the library 'std_logic_arith'. Try to use the more modern library 'numeric_std'. You will find more information about this on this website.

Best Answer

Related Solutions

Electronic – When to use STD_LOGIC over BIT in VHDL

Target type std.standard.bit in variable assignment is different from std_logic_1164.std_ulogic

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