Electronic – STM32 SPI slave: Reset DMA state on high NSS

I'm trying to setup a STM32F303RE SPI2 slave that must continuously and repeatedly send contents of a 2-byte buffer using DMA.

More specifically, if my buffer is:

#define ALIGN(x)    __attribute__((aligned(x)))
ALIGN(4) uint8_t TxBuffer[2] = { 'A', 'B' };

then I want my STM board to behave in the following way:

1. if master sends it 2 bytes, it should always send back 'AB'
2. if master sends it 1 byte, it should always send back 'A'
3. if master sends it N>2 bytes, it should always send 'AB' N/2 times + a trailing 'A' if N is odd

Since I'm a beginner with this, I decided to start with a simple implementation and build on that along the way. Which is why I'm using DMA without interrupts. Here's how the (relevant) code currently looks:

/* TX & RX buffers for SPI. */
ALIGN(4) uint8_t        TxBuffer[2];
ALIGN(4) uint8_t        RxBuffer[2]; /* Dummy, not actually used. */

int main(void)
{
    SPI_Config();
    SysTickConfig();

    RxBuffer[0] = (RxBuffer[1] = 0);
    TxBuffer[0] = 'A';
    TxBuffer[1] = 'B';

    while (1)
    {
        /* Clear DMA1 global flags */
        DMA_ClearFlag(DMA1_FLAG_GL4);
        DMA_ClearFlag(DMA1_FLAG_GL5);
        /* Disable the DMA channels */
        DMA_Cmd(DMA1_Channel4, DISABLE);
        DMA_Cmd(DMA1_Channel5, DISABLE);
        /* Disable the SPI peripheral */
        SPI_Cmd(SPI2, DISABLE);
        /* Disable the SPI Rx and Tx DMA requests */
        SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE);

        DMA1_Channel4->CNDTR = (DMA1_Channel5->CNDTR = 2);
        DMA1_Channel4->CPAR = (uint32_t) &SPI2->DR;
        DMA1_Channel5->CPAR = (uint32_t) &SPI2->DR;
        DMA1_Channel4->CMAR = (uint32_t) &RxBuffer[0];
        DMA1_Channel5->CMAR = (uint32_t) &TxBuffer[0];

        /* Enable the SPI Rx and Tx DMA requests */
        SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE);
        /* Enable the SPI peripheral */
        SPI_Cmd(SPI2, ENABLE);
        DMA_Cmd(DMA1_Channel4, ENABLE);
        DMA_Cmd(DMA1_Channel5, ENABLE);

        /* Wait the SPI DMA transfers complete */
        while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET) {}
        while (DMA_GetFlagStatus(DMA1_FLAG_TC5) == RESET) {}
        while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET) {}
        while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET) {}

        // Here RxBuffer data can be inspected
    }
}

static void SPI_Config(void)
{
    GPIO_InitTypeDef GPIO_InitStructure;

    /* Enable SCK, MOSI, MISO and NSS GPIO clocks */
    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB , ENABLE);

    /* SPI pin mappings */
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_5); // SPI2_NSS
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_5); // SPI2_SCK
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_5); // SPI2_MISO
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_5); // SPI2_MOSI

    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_DOWN;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

    /* SPI SCK pin configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
    GPIO_Init(GPIOB, &GPIO_InitStructure);

    /* SPI  MOSI pin configuration */
    GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_15;
    GPIO_Init(GPIOB, &GPIO_InitStructure);

    /* SPI MISO pin configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
    GPIO_Init(GPIOB, &GPIO_InitStructure);

    /* SPI NSS pin configuration */
    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
    GPIO_Init(GPIOB, &GPIO_InitStructure);

    /* Enable the SPI peripheral */
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);

    /* SPI configuration -------------------------------------------------------*/
    SPI_I2S_DeInit(SPI2);
    SPI_StructInit(&SPI_InitStructure);
    SPI_InitStructure.SPI_Mode = SPI_Mode_Slave;
    SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
    SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
    SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
    SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
    SPI_InitStructure.SPI_NSS = SPI_NSS_Hard;
    SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;

    SPI_Init(SPI2, &SPI_InitStructure);
    SPI_CalculateCRC(SPI2, DISABLE);
    SPI_TIModeCmd(SPI2, DISABLE);
    SPI_NSSPulseModeCmd(SPI2, DISABLE);

    /*
     * SPI_I2S_FLAG_RXNE flag should be set as soon as 1 byte (quarter buffer)
     * is shifted into receiving FIFO.
     */
    SPI_RxFIFOThresholdConfig(SPI2, SPI_RxFIFOThreshold_QF);

    /* Enable the DMA peripheral */
    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);

    /* DMA Configuration -------------------------------------------------------*/
    DMA_DeInit(DMA1_Channel4);
    DMA_DeInit(DMA1_Channel5);
    DMA_StructInit(&DMA_InitStructure);
    DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &SPI2->DR;
    DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
    DMA_InitStructure.DMA_MemoryDataSize =  DMA_MemoryDataSize_Byte;
    DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
    DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
    DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
    DMA_InitStructure.DMA_Priority = DMA_Priority_High;
    DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
    DMA_InitStructure.DMA_BufferSize = 0;
    DMA_InitStructure.DMA_MemoryBaseAddr = 0;

    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
    DMA_Init(DMA1_Channel4, &DMA_InitStructure);

    DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
    DMA_Init(DMA1_Channel5, &DMA_InitStructure);
}

This works ok if master always sends an even number of bytes per chip-select (NSS pin). If the master only sends one byte @ some point (within a single chip-select) things start to get messy.

Here's a concrete scenario:

• STM32 board starts
• Master sends 2 bytes in a single chip-select and reads back the 2 bytes it received from slave's end. As expected, these are 'AB'.
• Master sends 1 byte in a single chip-select and reads the byte it received from the slave. As expected, this is 'A'.
• Master sends 2 bytes in a single chip-select and reads the 2 bytes it received from slave's end. This time those 2 bytes are 'BA'. As per the above stated conditions (1-3), I want them to be 'AB' instead.

What must I do to achieve this? I noticed "while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET)" never finishes when the master sends just the single byte, so I'm guessing that behind the scenes the DMA simply always waits for 2 bytes per-transfer (i.e. before setting TC), regardless of the state of NSS (chip-select).

Somehow I want to force DMA completion when NSS is high again (i.e. when the SPI slave is not chip-selected anymore).