I'm trying to generate a 24MHz clock signal from the STM32F407 running at 168MHz. This signal would then be used to clock a USB hub IC (Microchip USB2513B). From the hub's datasheet, I learn that the clock frequency should be 24MHz ±350ppm and the jitter less than 100ps RMS.
My question: would a clock signal generated by a timer fit with these specifications? I know that I can generate a 24MHz signal using a period of 7 (168/7=24MHz) but I wasn't able to find anything about timer accuracy and jitter in the STM32F407 datasheet.
Another potential option would be to use the Microcontroller Clock Output functionality but I would have to lower the system clock to 120MHz since the prescaler is limited to 5 for this feature (120/5=24). Again, I couldn't find any information on the accuracy and jitter of the MCO.
Third option would be to use a 24MHz crystal as a source for both the STM32F4 and the USB hub. If possible, I'd like to keep the 8MHz crystal I have now.
Does anyone know more about timer precision on the STM32F4 series?
EDIT: I found the main PLL jitter (15 or 25 ps RMS) but nothing about the accuracy.
I'm not sure if my reasoning process is sound, but assuming I use a 8MHz crystal as oscillator for the STM32F4, I guess that at best I can expect 3x the accuracy/jitter of my crystal?
Best Answer
PLL is just a frequncy multiplier, output frequency static relative accuracy is just the same as your crystal e.g.
\$3\times (8\,\text{MHZ}+1\,\text{ppm})=8.000008\,\text{MHz} \times 3= 24.000024\,\text{MHz} = 24\,\text{MHz}+1\,\text{ppm}\$.
Output jitter is depends pretty much on PLL closed-loop bandwidth and power spectral density of timebase oscillator jitter but, long story short, PLL will anyway remove components above its closed-loop bandwidth and hence reduce -or at least do not increase- input jitter