Electronic – store word assembly instruction in risc-v

$s and $t are register specifiers. Your interpretation MEM[RegisterData(s) + offset] is basically correct. $s means, essentially, "get the data out of register number s in the register file." So if s in the instruction is the bit pattern 10001, then $s means: read the value out of register 17, add the sign-extended offset bits (the 16 bits represented by i in the encoding), and use that as the address to access the memory. Similarly for the $t in the lw instruction. It means write the data back into the register numbered t.

Your question about sign extension: look up two's complement. The 16 bit two's complement number 0000 1111 1111 1111 is decimal +4095. The 16 bit two's complement number 1000 1111 1111 1111 is decimal -28673. The 32 bit two's complement number 0xffff8fff is also -28673. The 32 bit two's complement number 0x80008fff is decimal -2147446785, which is clearly not what you want.

I believe it is a bitwise and immediate AND.

You had the first two steps right:

OX3062FF80
0011 0000 0110 0010 1111 1111 1000 0000

But not the rest.

First separate out the opcode, starting from the left. All opcodes are 6 bits.

So the opcode in binary, from the left, is:

001100

which is 0xC. This is an andi instruction.

Then you need to separate out the fields according to the MIPS I instruction format;

001100  00011  00010  1111 1111 1000 0000 

opcode    rs    rt        immediate

Opcode:     0xC
rs:         0x03
rt:         0x02
Immediate:  0xFF80

I wrote some code and checked that an adi instruction has the above format in a disassembly listing.

To convert this into a assembly instruction:

The assembly language format of an andi is:

andi,rs,rt,IMM

Looking up the MIPS registers for the rs and rt fields:

rs = 0x03 => $v1
rt = 0x02 => $v0

so the corresponding assembly instruction is:

andi $v1,$v0,0xFF80