I am working on a design which involves an FPGA having an external clock, the clock source is supposed to be programmable clock synthesiser, however this needs to be programmed at power on by the FPGA to output the correct clock frequency. I don't have great experience in this domain, but I am kind of sure that the FPGA will not operate correctly without an appropriate clock.
My solution to this is to use a 125MHz crystal, which is connected to a programmable clock multiplexer. At power on the FPGA will receive the clock from the oscillator, after this it will program the clock synthesiser and switch the clock source on the clock multiplexer. The purpose of this is to have a precise phase synchronised system. My BIG issue with this is that I don't know if it is safe to disrupt the clock being delivered to the FPGA and if it will remain operational during this switchover phase. Hopefully someone may have a better idea of how FPGA's behave with regards to the clock.
The FPGA in question is a Xilinx ZC7Z010 Cortex A9. I am welcome to other ideas, but the FPGA most certainly needs to be clocked by an external oscillator.
Many thanks for reading this.
Best Answer
By the sounds of it you need to split your design up a bit more. Here's how I would do it:
Run the logic that does the clock configuration on a different clock domain entirely. FPGAs frequently have some low quality internal oscillator which will be available after power on. Use this clock for driving the logic that configures the clock generator.
Feed the logic that runs off the clock synthesiser directly from the synthesiser - don't put a multiplexer in the path (well you can, but you don't need to).
At power on, keep everything in reset except the logic in (1). Once the clock generator has been programmed, bring the rest of the logic out of reset.
As long as you remember to add a clock resynchronisers for signals/flags that go between the two clock domains, you should be fine.
It's frequently the case in FPGA designs that you will essentially have a "management" section of the design that runs off a free-running clock source which is always available. The management hardware is there to get everything ready after the FPGA is configured - things like preparing clock sources, PLLs, and so forth. You can then use that core to bring everything else out of reset once everything is prepared.