Electronic – Switching tone on and off at 120 bpm not working

clockfpgasoundverilog

I am trying to make a design that toggles a sound at a rate of 120 BPM (once every .5 seconds), and I am using a 50 MHz clock. Here's the tone module:

module tone(
input clk, 
input enable,
output reg speaker);

parameter clkdivider = 25000000/440/2;

reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider-1; else counter <= counter-1;

always @(posedge clk) if(counter==0) speaker <= enable ? ~speaker : 0;
endmodule

and here's the toggling module:

module lockstep_main(input clk, output speaker);

reg enable;

tone(.clk(clk), .enable(enable), .speaker(speaker));

parameter beat = 50000000/2;
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= beat-1; else counter <= counter-1;

always @(posedge clk) if(counter==0) enable <= ~enable;

endmodule

As it is, the design doesn't work properly, just causing the speaker to emit garbled tones. Also, if I try setting the enable register to 1 initially and not changing it, I still get no sound. What could be the issue here?

Best Answer

50000000/2 requires 25 bits, not 15 (log base 2 of 25000000 is 24.575, the ceil of that is 25). In the second module, counter gets set to 30783 instead of 25000000 so the 'BPM' is ~97456 instead of 120.

Related Topic