Electronic – Termination for backplane

pcbterminationthevenin

I'm developing on a small modular computer system using the Z80 just for fun. The backplane is a prototype PCB with five DIN41612 connectors wired in parallel, running about six inches from the first connector to the last. (This one: http://www.busboard.com/BB3U)

The CPU card I've made is composed of 74HCT-series logic and CMOS components (for SRAM, Flash, Z80, UART, etc.) all running at 5V. What kind of termination on the backplane would be ideal for a system like this?

The fastest signal on the bus is a 20 MHz system clock, everything else is in the 5 MHz range. The signals are mostly unidirectional, a few bidirectional for the data bus, and then some open drain signals for reset and interrupts inputs to the CPU card.

I've read about the VME bus which used Thevenin termination and it required strong drivers (74F-series to sink/source 24mA) over a very long backplane so that seems inappropriate here. But I'm not sure what else is appropriate.

Best Answer

Transmission line effects create false transitions from ringing when the Return Loss or Impedance mismatch occurs from time delays greater than the rise time.

Generally 74HCT logic is rated with 50pF and Vol rated at 4mA for some Vol like 0.4Vmax with an input threshold of 2 TTL diode drops or 1.4~1.5V and may have a rise time of 15ns @ 50pF over all temps but best case may be faster.

Using impedance of the back plane tracks to ground, you can compute the track capacitance and also compute the time delay and decide what is worse.

1) High impedance stripline with lower capacitance but higher inductance and high mismatch ?
2) Low impedance ( 50~100 Ohms) with high capacitance going at 2/3c velocity with matched terminations..

Use a track capacitance , impedance, prop delay calculator and use a 74HCTxx driver impedance of 50 to 100 Ohms with an RC rise time to estimate if rise time is > time delay.

If you do need termination it still becomes a tradeoff but will likely be an R pair network resistor DIP or SIP or SOIC that biases to 1.5V with some impedance unless you choose 74ACxx or other family.

As your backplane is edge sensitive such as going to counters , latches, you will want to compute noise margin in the clock drivers.

I suspect the rise time is too slow, but they don't give best case specs.

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Electronic – SPI multiple slave termination

SPI allows the so called "Daisy-Chain" and multi-slave topology. You seems to need multi-slave. Note that altough you will need a separate signal for the CS pin of every chip, you can share the MOSI/MISO/CLK pins between your nodes.

For your parameters, I think that a proper routed board will suffice since you are not working at high clock/signal speeds.

I never heard of SPI pins being terminated. You must indeed take care of grounding and avoiding short-circuits.

Note also, that I2C looks like a more appropriate solution for connecting several devices in a BUS (altough with less speed).

You can have your setup like this:

HOST_MOSI -> DEVICE1_MOSI, DEVICE2_MOSI, ..., DEVICEn_MOSI
HOST_MISO -> DEVICE1_MISO, DEVICE2_MISO, ..., DEVICEn_MISO
HOST_CLK -> DEVICE1_CLK, DEVICE2_CLK, ..., DEVICEn_CLK

HOST_PIN1 ->DEVICE1_CS
HOST_PIN2 ->DEVICE2_CS
  ...
HOST_PINn ->DEVICEn_CS

You might want to read link 1.

Electronic – SPI bus connections – to loop or not to loop

Loop back? NO. If the line is long enough to need termination (longer than risetime*c/10 or so), then drive it strongly enough to end terminate it properly, and match the line and termination reasonably well. If the line is short enough not to need termination, then it won't need the 'extra' conductivity that you seem to be looking for with the looped back connection.

A series resistor? NO. That style of source-end termination only works for a single point receiver at the end of the line. At earlier points on the line, you get the worst possible waveform for your receivers, which is a step to half voltage, followed by a dwell, followed by another step to full voltage.

Best Answer

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Electronic – SPI multiple slave termination

Electronic – SPI bus connections – to loop or not to loop

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