Electronic – Termination resistors with DDR3, are they needed

The big advantage of DDR3 over DDR2 is that it allows the address/ctrl bus to use fly-by topology instead of balanced T. Fly-by is the recommended and easiest topology for DDR3. Balanced T is still possible for DDR3, but it is discouraged.

Write leveling and read leveling should indeed be able to handle your mismatched delays. That is not the problem here. You problem will instead be mismatched reflections, which will affect your signal integrity.

I recommend you solve the problem by switching to fly-by topology. It is explained a bit here: https://www.youtube.com/watch?v=7sxBBvF12JY

Trace length matching is important in DDR, DDR2 and DDR3, but the most important question is how closely do they need to be matched.

For DDR1, 2 and 3, each byte should be matched to the strobe, and the strobe needs to be matched to the clock. Address and control likewise have a relationship to the clock. Just how tight the matching is depends on your specific implementation and requires you to analyse the link timing budget (See Micron note TN4611). How tightly each match is to another group of a byte depends on whether you have multiple clocks available. Once more, this is part of the timing budget analysis.

DDR3 is somewhat easier to route than the earlier versions (due to a feature known as Write Levelling), but that does not mean you do not need to do a timing analysis.

If you are using an FPGA for the memory controller, keep in mind that the effective length from the pins or balls to the die can be measures in inches rather than a few thou, and this needs to be accounted for in the timing budget (some FPGA tools normally allow timing closure to take care of this internally, but you need to enable the feature. Not all tools can do this).

So - can you ignore the track length match for DDR itnerfaces? My answer is no; you can however, do no more length match than a shortest route provided it does not violate the timing margin for the interface.

I will note that the timing budget becomes easier to meet the shorter the interface; the timing budget is dominated by read timing which has both an outbound and inbound component. The shorter the interface, the lower the cumulative timing offsets.