I've been reading the document Spartan-3 FPGA Family Advanced Configuration Architecture and I'm having trouble figuring out what the address of the first LUT is. Can anyone point me in the right direction?
EDIT: I'm trying to setup a Spartan 3E. In order to configure the first LUT as a NOT gate and connect it to outside world, I need to know what value to send to the configuration so that LUT becomes a not gate connected to the pins on the IC that I want.
I am learning about FPGAs and I need to know how they work from the transistor up.
Best Answer
Learning how FPGA's work from the transistor up is very ambitious. There's a lot of stuff inside an FPGA, and for the most part you never have to understand it to the level of detail that you are seeking. In fact, it's probably better if you ignore that stuff at first and learn some practical FPGA stuff instead.
The reason why you don't need to know those fine details is because the FPGA compiler will do it for you. Using VHDL or Verilog, you tell the FPGA compiler what you want, and it figures out how to do it for you. You don't need to know what gets programmed into the LUT's, where that LUT is located, or how to route the signals to/from the LUT. This also helps when you move from one FPGA to another. A Spartan-6 has a different LUT architecture than the Spartan-3's, and you don't want to have to learn a completely new architecture for each chip you use.
Then, as you get into it more you will learn more of the internal workings of the FPGA. Not down to the transistor level, but you will learn about the different kinds of signal routing resources, RAMs, I/O Blocks, carry logic, etc. Knowing about this kind of logic will help you make better use of the FPGA-- making your logic smaller and faster.
One really cool way to find out about the internals of a Xilinx FPGA is to write some VHDL/Verilog code and compile it. Then using the Xilinx FPGA Editor to go in and examine what the compiler did, looking at signal routing, slice usage, LUTs, and Flip-flops. This is most useful for me in understanding why my logic was bigger than I thought it should be. I would guess that 95% of the time you don't have to understand the inner working of an FPGA in more detail than what FPGA Editor will give you.