This question is related to this one. But the focus is a little different so I put it here.
I tried to understand the detailed working steps of below circuit. It is an old 3T1C DRAM cell circuit. This picture is quoted from the book Memory Systems by Bruce Jacob.
I think the input capacitance of T2
is just a representation of the T2's characteristic, which is not a real capacitor
. I know that conceptually capacitance is defined as the ratio of q/V
.
My first 2 questions are:
-
Does this
input capacitance of T2
mean the ratio between the chargesq
and voltageV
required to open T2's gate? -
If the charges remain on T2, will T2's gate stay open?
Below is my understanding of the circuit steps:
I guess:
-
write rowline
is active-high -
read rowline
is active-high -
write bitline
is active-high -
read bitline
is active-low
Steps to Write and Read "1" to and from the cell
Steps:
-
write rowline
goes to high to signal the write operation. T1 is opened. -
write bitline
goes to high because we are writing1
. -
write bitline
reaches T2 through T1. T2 is charged and opened. -
write rowline
goes to to low to finish the writing. T2 is charged and opened. -
read rowline
goes to high to signal the read operation. T3 is opened. -
read bitline
reaches T2 through T3. -
Because T2 is opened in 3, 4, so
read bitline
further reaches ground through T2. Soread bitline
reads 0 (ground). -
Because
read bitline
is active-low, so the 0 voltage in 7 is interpreted as a logical1
.
Steps to Write and Read "0" to and from the cell
Steps:
-
write rowline
goes to high to signal the write operation. T1 is opened. -
write bitline
goes to low because we are writing0
. -
write bitline
reaches T2 through T1. T2 is not charged or opened. -
write rowline
goes to to low to finish the writing. T2 is not charged or opened -
read rowline
goes to high to signal the read operation. T3 is opened. -
read bitline
reaches T2 through T3. -
Because T2 is not opened in 3, 4, so
read bitline
reads the voltage ofread rowline
through T3, which is high. -
Because
read bitline
is active-low, so the high voltage in 7 is interpreted as a logical0
.
Am I correct?
Best Answer
It is the intrinsic gate capacitance of T2. It is where the bit is stored in this DRAM cell.
Yea, but there is leakage current and eventually capacitor will get discharged in order of milliseconds. This is the biggest drawback of DRAM cells.
Since we assume MOSFETs like switches here, it is more logical to use terms 'closed' for ON state and 'opened' for OFF state. You have used it the other way in your explanations.
There are some problems in steps 5, 6, 7, 8 of "Steps to Write and Read "0" to and from the cell" which seems like comes from the misunderstanding in MOSFET's switching operation.
After writing '0', the capacitor has discharged to zero and T2 is off now.
When
read rowline
goes high later, T3 remains off -- because T2 is off, and hence the source terminal of T3 doesn't pull to ground.Since both MOSFETS are off,
read bitline
is not pulled to ground either. Theread bitline
should already be pulled up to Vcc thru a pull-up resistor, and therefore it is read as 'high', which is then interpreted as logic '0'.