Can you post more details regarding the target frequency, jitter and loop bandwidth (required settling time)? Also, what kind of oscillator do you want to use (external with a DAC, with/without dithering?, an on chip digital counter/accumulator)?
If you're happy with a digital "oscillator" (i.e. an overflowing accumulator) and its jitter then the rest of the circuit can be fairly simple:
- a counter (PFD) counting number of cycles between the reference and the (optionally divided) PLL output,
- a digital filter - anything will do assuming it does the integration (an accumulator) and it has a zero (minus (or plus?) a scaled PFD output) to stabilize the loop, optionally one or more poles above the loop bandwidth to reduce the control value "ripple" at reference frequency (only matters if fref
- most significant bits of the digital filter output (DVCO control value) are given as an input to the overflowing accumulator (DVCO).
As for the loop bandwidth, if not enforced by settling time, decide it based on the noise contributions of all components.
- If the jitter comes mainly from the reference or from PFD - use a smaller bandwidth,
- If the noise comes from the oscillator - increase it.
In case if the reference signal is phase or frequency modulated - use a loop bandwidth lower than the smallest frequency of the signal modulating the reference.
Trickier techniques are used if the output frequency is close or equal to clock frequency and/or if the low jitter or very fast locking range is required. Maybe in your case they are not needed, besides they may not be well suited to an FPGA implementation.
These methods are used. The TI MSP430, for example, uses something they call a "modulator" which is essentially what you're talking about.
The main advantage is that that they are super simple and they can change their output frequency quickly (without any lock-time or whatever that PLL's require), and without any "glitches".
I'll also mention another method that you didn't mention (directly). It is, essentially, a super simple version of making your approaches 3 and 4. It's called a numerically controlled oscillator. Here's a code snippet in VHDL (but it's generic enough that most should be able to follow):
signal phase :std_logic_vector (n_bits-1 downto 0) := (others=>'0');
process (clk_in)
begin
if rising_edge(clk_in) then
phase <= phase + inc;
end if;
end process;
clk_out <= phase(phase'high);
Basically, we have an n_bit long accumulator (a.k.a. counter). On each clock, we add 'inc' to the accumulator. The most-significant-bit of the accumulator is output as the new clock signal. The output frequency is calculated like this:
Fout = Fclk_in * inc/(2^n_bits)
Where Fclk_in is the input clock frequency, inc is the value added to the accumulator, etc. Fout can be anything less than Fclk/2. For more accuracy, or a lower output frequency, you need more n_bits.
The output of this logic is essentially a jittery clock, where the jitter is about 1 clk_in period. The frequency and duty cycle will be dead-on (given n_bits and the clk_in period).
I have frequently used this logic to generate baud rates and other slow but accurate clocks. Since I work with FPGA's and not too many ASIC's I normally keep the logic synchronous with respect to clk_in and output a clock enable signal or something-- but the same concepts apply.
Best Answer
A PLL controls a voltage-controlled oscillator in order to bring its frequency (or some derivative of it) into phase (and frequency) lock with a reference signal.
PLLs have many applications, from creating a "clean" replica of a noisy reference signal (with amplitude and phase variations removed), to creating new frequencies through multiplication and division, to demodulating phase- and frequency-modulated communications signals. The input-to-output transfer characteristics of a PLL can be controlled through the design of its feedback network.
A DLL controls a voltage-controlled delay line, which typically has many taps, in order to bring one of those taps into phase alignment with a reference signal. The input to the delay line is usually also the reference signal, so the various taps provide additional signals that are interpolated and/or extrapolated from the period of the reference signal.
DLLs are commonly used in high-speed communications among chips on a board (e.g., between a memory controller and its SDRAM chips) in order to "cancel out" things like input and output buffer delays as well as wiring delays, allowing very tight control over setup and hold times relative to the clock signal. This allows data rates to be much higher than would otherwise be possible.
With suitably-designed phase detectors, both PLLs and DLLs can work with nonperiodic reference signals; a common application involves aligning data signal transitions with a reference clock.
While the mentioned above (i.e. clean version of signal -> PLL) a key aspect of where PLLs/DLLs differ is that PLL's filter and effectively block jitter in the source from affecting the VCO output, whereas DLL's propagate jitter. At first this may appear to be a negative aspect of DLL's but it can be used to great effect. In some cases you need to pull the main sampling point from the signal that is arriving and ignore the jitter in the signal, you would use a PLL. In other cases, say when a signal and clock signal are subjected to the same jitter inducing effects either at the source or in the communications channel. You can use a DLL and multiple sampling delay times to reduce/eliminate the relative jitter between the two signals (because they have the very similar jitter) and use the delayed clock to align to an ultimate sampling point.