Electronic – the difference between scalar array and vector array

verilog

First question

Whether we declare the array as scalar or vector, we can access each element bit by bit. For example, we can declare two arrays below.

reg scalar_array[0:9];
reg [0:9] vector_array;  

always @*
begin
  scalar_array[0] = 1'b1;
  vector_array[0] = 1'b1;
end

I would like to know if the difference exists between two declarations.

Second question

Also, when I declare the two-dimensional array like below, I could access the entire row using the indexing operator[] for the variable declared using a below syntax.

reg[X:X] var_name [Y:Y];

However, I couldn't access the entire row when I declare the array using the below syntax.

reg var_name [X:X][Y:Y];

I would like to know how this concept can be synthesized on the hardware, and if they are both synthesizable, what is the difference between them.

reg [0:9] vector_array_2d [0:15];
reg scalar_array_2d[0:9][0:15];
always @*
begin
  vector_array_2d[0] = 'd1;
  scalar_array_2d[0] = 'd1; //raise the error!! 
end

Best Answer

For your first question, search for the difference between packed and unpacked arrays.

Your second question is a Verilog limitation with unpacked arrays - it only allows access to one array element at a time. SystemVerilog does not have this restriction. You can access an unpacked array as a whole, or select an entire dimension.

Related Solutions

Electronic – the difference between reg and wire after synthesizing

Neither of your examples will contain any latches or flip-flops. The always block in your second example is combinational, not sequential (if it were to synthesize a latch, what clock would control that latch?). You have to use a reg type for y simply because it appears on the left side of an assignment statement inside an always block. Many people consider this a disadvantage of Verilog, which is hard to argue with. In VHDL, a signal type would be used instead of both wire and reg, removing the confusion.

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

Related Solutions

Electronic – the difference between reg and wire after synthesizing

Electronic – Verilog asynchronous reads of regs – and design question

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