Electronic – The flash of STM32F10x cannot run at 24MHZ without latency stably


A board with STM32F103C8T6 sometimes runs into hard fault handler.

When I heat up the board to 65C or higher, a hard fault will be caused randomly, which leads me to check if the latency of the flash is not enough.

Then I set the flash latency to 1 clock, the problem is solved,the chip runs stably even when I heat it up to 100C.

But it makes no sense because CPU runs at 24MHZ(HCLK is 24MHZ), which means no flash latency is needed as the datasheet says.

Here are my detailed clock configuration:
Clock source is 16MHZ given by external crystal, and PLL is 3x(I need to use USB ,so a clock of 48MHZ at SYSCLK is needed), then the AHB prescaler is configured to 2, so the clock of the CPU is 24MHZ.

I looked up the datasheet and it doesn't say clearly where the flash is clocked, but it says "Flash memory instructions and data access are performed through the AHB bus", does it mean the clock of the flash equals to AHB (24MHZ in my application)? But it doesn't work stably, where am I wrong?


Best Answer

The description of the Flash access control register (FLASH_ACR) (Page 59 of the manual here) states:

Bits 2:0 LATENCY: Latency
  These bits represent the ratio of the SYSCLK (system clock)
     period to the Flash access time.
  000 Zero wait state, if 0 < SYSCLK≤ 24 MHz
  001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
  010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz

So it looks like the flash is referenced to SYSCLK which you have at 48MHz.