I have a ton of 2N3904 transistors and would like to use them for my RTL logic project. Based on what I could figure out on the web, and the parts I had, I've gotten logic gates to work quite well with the following values:
simulate this circuit – Schematic created using CircuitLab
Although this works fine, I'm a bit concerned about what I've read on the data sheet for the 2N3904. It states that the Base-Emitter Saturation Voltage has the following specs:
Ic = 10mA
Ib = 1.0mA
Ic = 50mA
Ib = 5.0mA
I'm having a hard time understanding what that means exactly. If you calculate the current for the base input with Ohm's Law, we get I = 5 / 10000 = 0.0005. Am I correct that this is 5mA? I replaced R2 with a 5K resistor and it switched the same, which would be 0.001 or 10mA.
Like I said, it is working at the moment. I just want to make sure that I purchase the right resistors for the job. I know that the goal is for the transistor to be fully saturated, however I don't know if this is how that is done or not.
Thanks,
Best Answer
Every transistor has a current gain, usually \$\beta\$ or \$h_{fe}\$ in the datasheet. Typical values are on the order of 100. When the transistor is not saturated, then the base current and collector current are related by this factor:
$$ I_c = h_{fe} I_b $$
When the base current increases to the point where collector current can increase no more, the transistor is said to be saturated. The collector current can increase no more because it can't permit any more current -- the current is entirely limited by R1 in your diagram, and the voltage from emitter to collector is at a minimum.
When we design digital logic, we don't want to just barely saturate the transistors. We want to saturate them a lot. This provides some extra margin against variations in \$h_{fe}\$, and also takes into account that for higher frequencies (necessary for quick high/low transitions), \$h_{fe}\$ is effectively reduced.
Rule of thumb: in digital logic, design for a collector current 15 times greater than the base current.
So here, you've selected a collector resistor of 1kΩ. At saturation, the emitter-collector voltage is much less than the supply voltage, so we can estimate the collector current as:
$$ I_c = \frac{5\mathrm V}{1\mathrm k\Omega} = 5\mathrm{mA} $$
We want the base current to be 1/15th that (0.33mA), and the voltage across the base resistor will be the supply voltage, less about 0.65V from the base-emitter junction of Q1. So:
$$ R_2 = \frac{5\mathrm V - 0.65 \mathrm V}{0.33\mathrm{mA}} = 13 \mathrm k \Omega $$
Your selection of 10kΩ is close enough.
You can also scale the resistor values up, maintaining the ratio of base to collector current, but reducing the current overall. That reduces your power consumption, but also reduces the logic speed as the smaller currents are able to charge the parasitic capacitances less rapidly. This is a performance vs. power consumption trade-off that you get to make as the engineer.