1st check the reference design for layout coupling , isolation and grounding requirements.
Then try to fit on 1 layer with wire jumps, using all SMT and power/ ground fills and beefy driver tracks, then 2layer if necessary for low density boards. Add extra pads for spare chips, caps, polyfuses, connectors, test points.
A pro layout designer for logic may use orthogonal signal layers with separate power ground layers and understand the impact on signal skew, track impedance and ground topology for analog and digital.
A good Test Engineer with define the requires for test nets, testability, and all the DFT specifications. A good Process Engineer knows the IPC pad requirements for wave and reflow are different and how to design the solder mask and component orientation deign rules. A component Engineer knows how to reduce costs on component selection which impacts layout. A mechanical engineer understands the stress on solder joints from warp , shadow effects of big near little parts and an industrial engineer also understands how the ground fill affects reflow thermal profiles and instrument designers will understand how to construct differential pairs with guarding, and signal decoupling from high current switched power tracks. An RF engineer knows how to specify copper geometry with layout. A good cost/quality engineer will know how to choose feature specs from all suppliers under consideration.
A great PCB designer knows all of this and more. You can start with reading about DFM, DFT, DFC,or DFX and borrowing IPC stds from somewhere. ($$$)
High voltage clearance is a complex subject. Too many factors and standards to consider.
In your case, I'd follow the IPC-2221A "Generic Standard on Printed Board Circuit".
According the table 6-1. "Electrical Conductor Spacing" for a 80V difference between conductors we have:
Internal layers --> 0.1mm (3.9 mils)
External layers uncoated -->0.6mm (24 mils)
External layers coated --> 0.13mm (5 mils)
IPC-2221A is a proprietary standard and I can´t reproduce the whole table here.
These numbers are not mandatory, they just stated a minimum clearance. I would use bigger numbers.
Note, as it´s said before, the high power vias. They should keep the clearance in the "low voltage" side.
The stackup seems to me quite sensible but keep in mind the pins in the High power THT components. They should keep the clearance.
Best Answer
Hopefully, by the time you get to this point you'll have a pretty good design. Your PCB is fundamental to the schematic despite it never appearing on it (well maybe fixing holes etc). The PCB touches every single electronic component in your design - very important to do the job to what was agreed on day 1 (or amended via the process).
I'll also add that this is just off the top of my head and, there are plenty of variations on this such as when designing specifically for an end user - obtaining customer approval at several points along the way is a necessary part of the process and this should be agreed up-front. Also, some products require 3rd party independent testing to "prove" they comply with regulations such as EMC, safety etc..
Between #5 and #6 it is worth mentioning that bread-boarding certain parts of the design may be done where it is felt that the simulation may not give the full picture. This is definitely not uncommon and, designing a PCB just to rigorously test certain parts of a design, is a valid step along the way even though the bread-board/PCB may never get used on the "real" job.
Before #15 you should also start to consider (when production run quantities are not trivial) placing orders for production parts taking into account lead times. You should also be starting to think about any special test fixtures that need to be introduced and doing this in enough time so that the first proper production run is not delayed.