I'm hoping to be able to output HDMI/DVI-D for my next FGPA project but my FPGA doesn't have native support for TMDS outputs. The FPGA is a Spartan 3E and I believe it only has support for LVDS differential signalling.
I read a lot online about differential signalling and I have a general idea of how it works but I am confused about the different standards. I have also gone through the specifications for HDMI but it's very dry and seems to presume a certain familiarity with these concepts beforehand which I don't have.
For example, what exactly is TMDS vs LDVS? Is TMDS just an encoding scheme run over LVDS? Are TMDS and LVDS just standards for differential signalling but with different electrical characteristics? The absence of search results for LVDS to TMDS converter chips suggests my understanding is broken here.
In a practical sense, I am wondering if I can simply wire an HDMI breakout board directly to the input pins of my FPGA, configure those pins to the LVDS IO standard and expect it to work (given that the software side is written correctly). Some websites imply that I can but it seems that their FPGAs all have built in TMDS drivers where mine doesn't. Other sites say that I need TMDS support but then go onto say that LVDS works too. Wikipedia seems to suggest that LVDS is being phased out as a standard for transmitting data over DVI or HDMI.
Can anybody help me clear up any misunderstanding on how all this works?
Best Answer
Good questions. I have been researching this topic myself recently, and will try to provide some brief answers here.
LVDS (low-voltage differential signaling) is simply an electrical specification for a differential signaling interface, while TMDS (transition-minimized differential signaling) is both an electrical specification AND a specific 8b/10b encoding scheme. Unfortunately, the electrical specifications are not directly compatible, although there are various ways to "adapt" one to the other under certain circumstances.
Electrically, LVDS uses totem-pole drivers and differential termination (100-120Ω), while TMDS uses CML (current-mode logic) open-collector drivers and individual 50Ω terminations to +3.3V. The Spartan-3E IOBs do not directly support CML.
Then there's the question of TMDS coding. The Spartan-3E IOBs have support for DDR, with data rates up to 628 Mb/s, but no dedicated high-speed SERDES logic. You would have to do the TMDS encoding and decoding in the FPGA fabric, using the DDR support in the IOBs to get the final bitstreams. This would limit you to pixel rates of 62.8 Mp/s or less.
No, not on the input side, at least not without some effort to terminate the TMDS properly and then AC-couple it with proper bias to the LVDS receivers on the FPGA (all of this while maintaining an accurate 100Ω differential impedance). Note that the sample projects you link to are all output-only examples. Driving DVI/HDMI from an LVDS output seems to be much more forgiving; they don't seem to have added any bias or termination resistors to their PCBs.
Your best bet would be to use external DVI/HDMI input and output chips, and make the connection to the FPGA via their parallel buses. I have used Analog Devices parts in the past.