If I understand correctly, you are looking for an analog multiplexer with the option of setting the channels to high impedance.
If so, the 4052 or 4053 should do the job, they have an enable input which sets the ports to high impedance.
As mentioned in the comments, it might be a good idea to post a rough schematic of what you are doing, as it's a little unclear at present.
In general, it is possible and quite common to use back-to-back three-state buffers for bidirectional bridging. Such bridges, however, need something to tell them when they should conduct in each direction. For example, in many microprocessor systems, the processor will sit on a local data bus along with its memory, and that will be connected to a system data bus through such a bidirectional bridge consisting of back-to-back three-state buffers (the most commonly-used chips for such purpose would have 8 back-to-back pairs of 3-state drivers, but it would be possible to use chips with unidirectional 3-state drivers and wire them back to back). When the processor wants to write data to the external bus, the drivers are enabled in one direction. When it wants to read data, they are enabled in the other direction.
Such devices work very well in situations like microprocessor buses where there are pre-existing signals that specify which direction they should operate. They will not be sufficient for something like a full I2C implementation, in which the direction of of the clock wire may reverse without any transitions on it. To clarify, a data read or slave-acknowledge clock cycle on I2C behaves as follows:
- Master asserts SCK (drives it low)
- Slave sees SCK asserted, and starts driving it low as well
- Slave determines whether it should assert or release SDA (may be instantaneous, or could take hundreds of microseconds)
- Slave asserts or releases SDA as appropriate, and releases SCK
- Master sees SCK released and processes data on SDA
It is imperative that the slave's SCK wire not be released until the master decides to release it, and also that the master's SCK wire not be released until the slave decides to release it. It is not possible to accomplish this with conventional logic, since there would be no way of knowing whether either side had released SCK without releasing SCK to that side. Philips in their I2C bridging chips gets around this by using chips that process multiple logic levels. Essentially, what happens is that when the SCK wire on either side is driven "hard" low, the SCK wire on the other side will be driven low, but somewhat less strongly. Strongly enough that attached devices will see the signal as a low, but weakly enough to be distinguished from an externally-driven strong low.
Note that in scenarios involving a single master and not using clock-based handshaking, it may be possible to build an I2C bridge using only conventional logic levels, since the direction of the SDA wire would be well defined at all times, but keeping track of the I2C communication state would be sufficiently complicated that using an I2C bridge chip would probably be easier.
Best Answer
Boolean logic (propositional calculus) is an idealized, mathematical formal system which has exactly two variable values, True and False. The Boolean operators { AND, OR, NOT } are sufficient to synthesize any Boolean expression, and even the set of { NAND } by itself is also sufficient (since NOT X = X NAND X, A AND B = NOT (A NAND B), A OR B = (NOT A) NAND (NOT B)). But there is a missing piece if you're trying to model a tri-state system. There is no set of Boolean operators that can produce a value that is simultaneously not-True and not-False. A single Boolean variable must be either True or False, there is no such thing as a Boolean tri-state value.
In practical digital logic circuits, we map the Boolean True and False values to a range of voltages, such as a "logic low" (V < 0.7V) for Boolean False and "logic high" (V > 2.4V) for Boolean True. There is a range of voltages that has no defined logic value; this is an essential part of the "noise immunity" which is the primary advantage of digital logic.
What makes an output an output is its relatively low source impedance. Inputs are expected to draw negligible input current, so their input impedance needs to be fairly high (>6000 ohms). Outputs need to be able to drive the parasitic capacitance of wiring and PCB routes, so an output needs to be fairly low impedance (<100 ohms). But if the transistors that drive the output are "switched off", then the output pin is no longer driven by the output: that's what is meant by "high-impedance" or "tri-state".
At a system level, what happens when a device makes its output high-impedance (or tri-state), is not determined by the tri-state device but rather determined by other parts of the system. Usually there is a requirement for some passive termination to pull the signal to some predetermined level, like VDD/2, otherwise the voltage could drift into the logic low or logic high range. Typically the use case for tri-state logic is to allow more than one device to share the output driving capability, though not all can drive the output at the same time. This is closely related to open-drain outputs or open-collector outputs, which can only pull the signal to logic low but require an external passive device to make the logic high default signal when no driver is active.
There is a way to model tri-state output behavior, but it requires using two Boolean variables instead of one: one variable is used to enable the output, and when not-enabled, then the value of the pin is tri-state. This is not a Boolean value, it's a practical digital logic state represented by the combination of two Boolean variables.
The missing piece is called a transmission gate; the symbol is usually drawn like two intersecting triangles or a six-pointed star. See this answer: https://electronics.stackexchange.com/a/158244/35022 and What is this schematic symbol with intersecting triangles? This is not a Boolean operator, but it is one of the basic building blocks of digital logic, and it is controlled by a logical enable input. So it is possible to synthesize Boolean equations for output-value and output-enable, and then those two Boolean values control the transmission gate. If you wanted to synthesize a tri-state logic function in an FPGA, you could describe it using verilog, which supports 1/0/z wire values, and a typical FPGA would have low-level output pin primitives that have an output-enable.