I'm currently trying to understand the function of a loop filter. But where I'm stuck is that I know the output of the charge pump is a series of current pulses whose width is proportional to the amount of time that the there is mismatch between the reference and the VCO frequency. The problem I find is that each pulse can/should only occur at Fcmp right? So isn't it essentially just PWM? But at the same time, I've heard that the purpose of the loop filter is filter out jitter from the reference. But given that the frequency of the reference is pretty much fixed, I can only see it as an "integrator" or a crude A to D. So, I guess ultimately, what I'm asking is, what am I missing?
Electronic – Trouble understanding Loop Filter in a PLL
control-looppll
Related Solutions
Do you need a PLL? What are your distortion requirements, linearity of FM deviation versus input voltage? Don't rush off down the PLL route without having first looked at direct modulation.
Start with the specifications you require for the FM signal. Linearity and noise, as well as modulation bandwidth and deviation.
It is far simpler to modulate a VCO directly, lower power, if you can tolerate any tuning law non-linearity. Different VCOs have different linearity. A wide deviation VCO can be used in a small, nearly linear, part of its tuning curve.
Even if you've tried direct modulation and found it wanting, don't give up on it without a bit of investigation. I personally have used a VCO which had a kink in its tuning bandwidth curve at about 500kHz. The main LC tank tuning went via inductors, but the gain/sustaining tuning went via an RC. The manufacturer was persuaded to modify it to use inductors both both tuning points, which increased the flat bandwidth to more than 10MHz.
A colleague of mine made a TV transmitter exciter which started with two VCOs being modulated differentially and mixed, to get a low frequency, wide deviation, high linearity, low noise, wide bandwidth FM signal.
If you do end up using a PLL, then 10MHz bandwidth is fairly straightforward. You could use a digital phase detector. They don't quote a bandwidth, because it's as wide as permitted by the input rates, and limited by what you do with it afterwards. However, for wide bandwidths like 10MHz, I'd tend to use an analogue phase detector, an RF mixer with a DC-coupled IF. It's no faster, but is quieter and better behaved.
The CLTF can be unstable, it depends on the ratio of time constants. It's easier than you think to make a stable loop, and with minimal mathematics, and no Laplace functions.
First of all, short circuit any integrator capacitors in your loop filter, and open circuit any lowpass filter capacitors, so it merely becomes a gain of R2/R1. Now compute the gain round the loop. The frequency at which it becomes 0dB is your loop bandwidth. If you want a different loop bandwidth, alter the gain.
Note that the loop filter time constant plays no part in the selection of the loop bandwidth. It is solely the loop gain that sets this.
Now while the PLL you've created like this has the correct loop bandwidth, and is stable, it probably doesn't meet your specifications yet.
To improve low frequency tracking, put C back in series with R2, to increase the gain at low frequencies. This configuration is called a 'broken integrator'. Keep the C.R2 break frequency no higher than half your loop bandwidth. This will ensure that the phase shift it creates is small enough at your loop bandwidth frequency to maintain loop stability. If there's any tendency of your loop to vary the gain, perhaps with a VCXO with a non-constant tuning sensitivity, then this will vary the loop bandwidth, and may encroach on your low frequency break point, making the loop less stable, and ultimately unstable. Move the breakpoint down further if this is the case. Move it down to at most one third of your loop bandwidth if you're going to use high frequency filtering as well (next paragraph).
If you want to improve reference rejection, you can add a capacitor in parallel with R2, to roll off the loop response at high frequency. Keep the this break frequency at least two times the loop bandwidth if used by itself, or at least 3 times if used in conjunction with a broken integrator.
It might be worth revisiting your specification of 10Hz for loop bandwidth. If that's based on reference rejection, you will often get better loop dynamics with a wider loop bandwidth, with the addition of some high frequency roll-off to improve the removal of the reference modulation.
If you're familiar with a Bode plot, then sketch out what I've described.
Best Answer
The purpose of a PLL is to make the VCO track the reference at DC and low modulation frequencies, and to be unaffected by the reference at high modulation frequencies.
You can make a PLL from a PSD, a VCO, and some gain, nothing else is needed. Because the VCO is controlled by frequency, and its phase is detected, that makes the loop behave as an integrator. This makes the gain infinite at DC, so it tracks the reference, and falls to insignificance at very high frequencies, so rejects the reference modulation.
Adjusting the gain in the loop sets the frequency at which the closed loop gain becomes unity, which sets the loop bandwidth.
Now for the loop filter. Although this loop is stable, tracks at low frequency, rejects at high frequency, it's not very good. Most people who use PLLs want better low frequency tracking and better high frequency rejection than the single integrator of a PLL can achieve. So we add a loop filter.
The loop must remain stable. The VCO integrator gives us 90 degrees phase shift. The phase shift added by the loop filter must stay strictly below 90 degrees at the loop bandwidth, and ideally less than 40 degrees to maintain reasonable dynamics, we don't want too bouncy a response. This means that any low pass poles have to have break frequencies well above the loop bandwidth. These low pass poles improve the rejection of reference modulation at high frequencies.
To improve tracking at low frequencies, we use an integrator below the loop bandwidth. By itself, an integrator would add 90 degrees phase shift, guaranteeing instablity, so it's 'broken' with a zero (that's the resistor in series with the integrator capacitor) to reduce the phase shift at the loop bandwidth back into the stable region.