I'm trying to program my nexys 4 ddr board to receive 1 or 0 as ASCII charachters via UART and display it on one of its 7segment display ,the LED that shows when its getting data is flashing but it won't display any character, also i'm using tera term emulator to send the characters.If any of you guys have an idea why it isn't working please let me know. Here is my code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_arith.all;
entity seg is
Port (
i_clk : in STD_LOGIC;
i_rx_serial : in STD_LOGIC;
anod7 : out STD_LOGIC ;
anod6 : out STD_LOGIC ;
anod5 : out STD_LOGIC ;
anod4 : out STD_LOGIC ;
anod3 : out STD_LOGIC ;
anod2 : out STD_LOGIC ;
anod1 : out STD_LOGIC ;
anod0 : out STD_LOGIC ;
ca : out STD_LOGIC := '0';
cb : out STD_LOGIC := '0';
cc : out STD_LOGIC := '0';
cd : out STD_LOGIC := '0';
ce : out STD_LOGIC := '0';
cf : out STD_LOGIC := '0';
cg : out STD_LOGIC := '0';
dp : out STD_LOGIC := '0'
);
end seg;
architecture Behavioral of seg is
signal r_main : integer range 0 to 4 := 0 ;
--signal i_tx_byte : std_logic_vector( 7 downto 0 );
signal r_rx_data : std_logic;
signal o_rx_dv : std_logic;
signal r_clk_count : integer range 0 to 10416 ;
signal r_bit_index : integer range 0 to 7 := 0;
signal r_rx_byte : std_logic_vector( 7 downto 0 ) := (others =>'0' );
signal r_rx_dv : std_logic := '0';
signal verif : std_logic;
--transmisie
begin
--receptor
anod7 <= '0';
anod6 <= '1';
anod5 <= '1';
anod4 <= '1';
anod3 <= '1';
anod2 <= '1';
anod1 <= '1';
anod0 <= '1';
process(i_clk)
begin
r_rx_data <= i_rx_serial;
end process;
process(i_clk)
begin
if (i_clk = '1') then
case r_main is
when 0 =>
r_rx_dv <= '0';
r_clk_count <= 0;
r_bit_index <= 0 ;
if r_rx_data = '0' then -- conform protocolului uart detectarea bitului
0 este bitul de start
r_main <= 1;
else
r_main <= 0;
end if;
-- verificam mijlocul perioadei de un bit sa vedem daca este tot 0
when 1 =>
if r_clk_count = 5208 then
if r_rx_data = '0' then
r_clk_count <= 0 ;
r_main <= 2;
else
r_main <= 0;
end if;
else
r_clk_count <= r_clk_count + 1;
r_main <= 1;
end if;
when 2 =>
if r_clk_count < 10416 then
r_clk_count <= r_clk_count +1;
r_main <= 2;
else
r_clk_count <= 0;
r_rx_byte(r_bit_index) <= r_rx_data;
--verificam daca s au transmis toti bitii
if r_bit_index < 7 then
r_bit_index <= r_bit_index + 1;
r_main <= 2;
else
r_bit_index <= 0;
r_main <= 3;
end if;
end if;
--continua sa numere counterul si verificam cand bitul de stop ajunge la final
when 3 =>
if r_clk_count < 10416 then
r_clk_count <= r_clk_count + 1 ;
r_main <= 3;
else
r_rx_dv <= '1';
r_clk_count <= 0;
r_main <= 4;
end if;
when 4 =>
r_main <= 0;
r_rx_dv <= '0';
verif <= not verif;
when others =>
r_main <= 0;
end case;
end if;
end process;
process(verif)
begin
if r_rx_byte = "00110000" then
ca <= '1';
cb <= '0';
cc <= '0';
cd <= '1';
ce <= '1';
cf <= '1';
cg <= '1';
dp <= '1';
elsif r_rx_byte = "01100010" then
ca <= '0';
cb <= '0';
cc <= '1';
cd <= '0';
ce <= '0';
cf <= '1';
cg <= '0';
dp <= '1';
else
ca <= '0';
cb <= '0';
cc <= '0';
cd <= '0';
ce <= '0';
cf <= '0';
cg <= '0';
dp <= '1';
end if;
end process;
end Behavioral;
Best Answer
I made two categories of changes to your design in addition to reformatting it for easier readability.
The changes to seg (some of which are purely cosmetic):
In your source code there was part of a comment that was on it's own line although not preceded by "--".
Now testing it the modified circuit would either require a Nexys4 board (or other by setting the generic CLKS_PER_BAUD) or simulation.
Fortuitously having previously writtent a simple UART transmit and it's associated testbench, these were adapted to interface to your design:
The UART TX was modified to eliminate a parity bit (it's a simple, dedicated purpose design, using a baud rate clock).
When simulated the testbench demonstrates your design is functional:
Because your design has been modified to provide recognizable sequential logic constructs for RTL synthesis it should synthesize. It should be functional as long as the CLKS_PER_BAUD is the default value for the 100 MHz NEXYS4 board clock.
Your design should be functional using a clock as slow as 16 times the baud rate.
ISE and Vivado Documentation
Artix-7 devices from Xilinx such as that used on the Nexys4 board are supported by both ISE and Vivado.
For ISE the form of RTL description in VHDL to infer register based design can be found in Synthesis and Simulation Design Guide, UG626 (v 14.4) December 18, 2012, Ch. 5 Coding for the FPGA Design Flow, Registers in FPGA Design. Also see Latches in FPGA Design "Xilinx® recommends that you avoid using latches in FPGA designs, due to the more difficult timing analyses that take place when latches are used."
For Vivado Vivado Design Suite User GuideSynthesis UG901 (v2018.3) December 19, 2018, Ch. 4 HDL Coding Techniques, Flip-Flops, Registers and Latches, Flip-Flops and Registers Coding Examples. Also see Latches, "Inferred Latches are often the result of HDL coding mistakes, such as incomplete if or case statements." and "Vivado synthesis issues a warning for the instance shown in the following reporting example. This warning lets you verify that the inferred Latch functionality was intended."
The shown examples are a subset of those found in IEEE Std 1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis (now withdrawn), Section 5. Modeling Hardware Elements, 6.1 Edge-sensitive sequential logic which are all likely (still) supported if not shown in Xilinx documents. You'd also find 6.2 Level-sensitive sequential logic, for latches.