Electronic – UART shift registers

shift-register

Can I say that in UART shift registers –

UART Tx uses Parallel in Serial Out Shift registers – My reasoning is that we are writing complete byte but it will transmit bit by bit. True or False?
UART Rx uses Serial in Parallel out shift registers – My reasoning is that we are receiving data in Serial but we will read data in parallel i.e. after 1 byte. True or False?

Best Answer

Welcome Tannoy,

If you take the example of a microcontroller, Yes it happens what you told in point 1 & point 2. But along with data bits, there are some control bits also get transmitted and received.

Below is a block diagram of STM8 microcontroller UART unit.

STM8S reference manual (RM0016)

Related Solutions

Electronic – arduino – Sharing Clock and Data for 74HC595 and CD4021B Shift Registers

If I may answer my own question. It should work. Here's how with arduino over SPI.

void setup() {
    //Setup SPI
    SPI.begin();
    //Setup CD4021
    pinMode(CD4021_PSC_PIN9, OUTPUT);
    digitalWrite(CD4021_PSC_PIN9,HIGH);
    //Setup 74HC595
    pinMode(HC595_LATCH_PIN12, OUTPUT);
    digitalWrite(HC595_LATCH_PIN12,HIGH);
}

void loop(){
    //Shift out to 74HC595
    digitalWrite(HC595_LATCH_PIN12,LOW);
    SPI.transfer(BYTE_DATAOUT);
    digitalWrite(HC595_LATCH_PIN12,HIGH);

    //Shift in from CD4021B
    digitalWrite(CD4021_PSC_PIN9,LOW);
    BYTE_DATAIN = SPI.transfer(0x00);
    digitalWrite(CD4021_PSC_PIN9,HIGH);
}

Learned from here, from someone who has done this exact implementation before.

Electronic – Implementing feedback shift registers in a FPGA

1024 registers times 71 bits requires around 72k flip flops. In some cases the synthesis tools will play tricks to get the size down, depending on the tap locations. If you specify how many taps, it may be possible to get a better estimate. On Xilinx devices, you can fit a shift register of up to 32 elements on one LUT, but you don't get any taps in there. Best case would be 3 LUTs per shift register for 3072 total, assuming the taps are between 24 and 32 bits apart. Xilinx Spartan 6 LX75 would work for the raw flip flop count, Spartan 6 LX9 would work for best case LUT packing. You should probably throw together an implementation of the shift registers on a large Spartan 6 and see how much space it takes up and go from there. For the 7-series devices, the Artix-7 XC7A15T would be large enough for best case LUT packing, or XC7A75T would be large enough for raw flip-flops.

Best Answer

Related Solutions

Electronic – arduino – Sharing Clock and Data for 74HC595 and CD4021B Shift Registers

Electronic – Implementing feedback shift registers in a FPGA

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