So I am basically trying to grasp/confirm my grasp of SDRAM and DDR. So basically I understand that there is going to be some chips each with up to 8 banks (so kinda like 8 chips internally?). For each bank there is so many rows, than for each row there is a column or basically like a grid or 2 dimensional array specifying a bit.
But I understand that a DIMM and most memory controller bus is 64 bit? So How do I get a connection from the 64 (128 cause they are differential pairs) to the 8 or so chips/modules?
I know this is a little bit of a fuzzy question, I may not know enough to define a more clear question.
BONUS OFF TOPIC QUESTION: Also just if anyone knows, how is this memory exactly accessed from intel cpu? Is the memory controller (set of registers) configured with the timings and that memory mapped to the cpu's address space so that a memory address operand will automatically be translated into banks, rows, and columns all opaque to the cpu code?
Best Answer
DIMMs have 64 single ended data lines, and they will be divided up among the chips - say, 8 chips with 8 data lines each, or 16 chips with 4 data lines each, or perhaps on a small module you could have 4 chips with 16 data lines each. Super high density modules may even have 32 chips with 2 data lines each. Each data line will be connected to only one of the memory chips. The address, control, and clock lines will be connected in parallel to all of the chips on the module. Some modules will even have two ranks of chips that are connected in parallel to the data lines, only one of which can be accessed at any given time.