Let me start by saying that 7 cm is not a long distance to go for 40 MHz signals. I've ran double that frequently and didn't even break a sweat. Below is a list of issues that you need to consider when doing this:
Trace length: As I just said, 7 cm is not far. But look at your timing budget. If your budget is tight you might have to do something called "matched trace lengths", where every signal of your bus has the same length. Odds are that at 40 MHz you don't need this, but it is worth looking into.
Parallel traces: Try to keep some space between signals on this bus. This is super important for clock and control signals, and less important for data. A normal PCB might have 0.008 inches (0.2 mm) between traces, and you might consider doubling or tippling that. It is OK for them to be close for short distances, but the longer the traces the farther apart they should be.
Power/Ground Planes: Yes, have them. This is important. Run your traces on a layer that is adjacent to the power or ground plane. I am skipping over a LOT of details here that pertain to high-speed digital design. This is an area for you to learn more of in the future. If you can't have a power/gnd plane then your problem has gotten 10 times harder. Run a ground trace next to each signal trace and hope for the best!
Termination: Yes, use them! If the signals are going from one chip to another (and not connecting to more chips) then using source termination is the easiest. Normally that would be a 33 to 50 ohm resistor in series and located at the driver of the signal.
Decoupling caps: Make sure that all chips are properly decoupled. Then add decoupling caps near places where signals move through a via (no more than 1 cap every 3 square cm). Again, I am skipping details but at 40 MHz you don't need to worry that much.
Good questions.
1) Does REF_CLK must be routed without vias.
Whenever you see something like "must be routed without vias" without a good explanation, chances are that someone does not fully understand what is going on and just think that is a good idea.
One of several things may be the issue:
- Different trace impedance on different layers, which will cause reflections whenever there is a via.
- Reference plane problem, because the impedance between the power planes of the design is not low enough.
Both of these are easy to avoid and is good practice - often even required if you want to pass EMI tests, build a solid design etc.
So provided you do this, you can use vias without any issues. The faster the signals, the more careful you have to design the vias. I have previously written about how to design vias for 28+ GBps signals here.
2) Does REF_CLK need termination resistor?
Best thing to do here is a quick simulation with your favorite IBIS simulator - or have someone do that for you (sorry, these tools costs money - but are worth it).
If you have very fast edge rates, chances are you need a termination resistor if the trace is electrically longer than about 1/3 of the rise/fall time. Use simulation to be sure (unfortunately you did not provide enough information about your design, or I might just have done it right away).
3) Is 4mm difference in trace length @50Mhz acceptable?
Another good question. Look at the rise/fall times of your signal. If the electrical length of the rise/fall time is significantly longer than the trace length mismatch, this will work just fine. Actually it is a good practice not to overconstrain layouts, even though it is often possible to match trace lenghts within a very narrow tolerance.
Best Answer
In fact, if you are designing a digital circuit with clock frequencies below about 50 MHz, you almost never will have to do signal integrity analysis to get a working design. And if you know what you are doing it is possible to design up to 1 or 2 GHz by using "best practices" rather than complex simulations.
I worked in an organization doing 1, 2, and 3 Gb/s designs and never saw a signal integrity tool in use until 2005 or so. (Although full-blown 3-d EM simulation was very occasionally used for very sticky problems)
However as the number of high-speed nets in your design increases, it's not always possible to stick to best practices everywhere, and then a simulation is valuable to indicate how much you can get away with.
In contrast to what another answer said, SPICE and its derivatives are not well suited to this type of simulation. SPICE is designed for lumped-element analysis at the transistor level. In the situation you described you need to simulate a distributed element (a transmission line) and you're unlikely to have a transistor-level model of your source or load. Some SPICE-derived tools might have a signal-integrity tool bolted on, but it isn't typically what they're good at.
Signal itegrity tools generally use higher level models to reduce simulation time when simulating dozens or hundreds of distributed elements. And they can take inputs from IBIS models of the source and load ICs. These are standardized high-level macromodels that don't reveal details of the IC internals that the vendor might not want to share with all its customers.
Although I use Altium regularly I haven't used its signal integrity modelling tools. But from the description, they do seem to be IBIS-based rather than SPICE-like, so would probably work in many cases.
Another well-known tool is HyperLynx from Mentor Graphics. Cadence offers a tool set called Sigrity which I believe is similar but I have never seen or used.