What does -dB mean here for the current?
0 dBI is exactly 1 amp (not to be confused with dBi which is the gain of an antenna compared to the benchmark (i)sotropic antenna)
A current of 100 mA is -20 dBI etc..
So when you have decibels for current as the Y axis then it is implicit that they the Y axis is dB relative to 1 amp (or dBI).
One further thing to consider is that the graph may be plotting peak current and peak current is \$\sqrt2\$ times bigger (for a sinewave). Read the LTSpice help advice to know exactly.
I've just checked on google about usage of the term "dBI" as representing current and nothing comes up. You can find dBuA for dB relative to 1 uA but nothing seems to mention dBI - I'm interested if anyone can provide some evidence to substantiate the usage of the term "dBI".
Sure, dBV are used and this is quite common and one website I visited compared decibels for current and voltage by calling them dB(volts) and dB(amps) - maybe "dBI" just isn't used so as not to confuse folk with dBi?
Hierarchical or subcircuits are the same, after LTspice flattens the netlist. You can see this by checking Generate Expanded Listing
in the control panel, the Operation
tab.
The advantage hierarchical schematics have is the direct graphical access through the symbol editing, where you can open its contents as if it were a schematic, and easily probe voltages, currents, powers (needs the two Save subcircuit ...
options checked in Control Panel > Save Defaults
). You can also probe inside plain subcircuits, but you have to check the expanded listing in the error log; it's more cumbersome, but not impossible.
Overall, hierarchical designs are more user-friendly, but the disadvantage is the lack of encryption. Subcircuits can be encrypted to protect the contents, hierarchical designs cannot be. The expanded listing does not work with encrypted libraries, which is to be expected, therefore you are not able to save and plot internal quantities. Also, a subcircuit is more compact, typically one file, hierarchical schematics can be more than one. Oh, and you won't see nice yellow symbols...
Both ways, hierarchical and plain subcircuits, allow for external parameters to be passed on, such as your Vs={Vcc}
example.
None is faster or slower than the other in terms of computations for same designs, since, as I mentioned before, LTspice flattens the whole schematic into a netlist, which is nothing more than a programming language for SPICE.
Which one to use? Take your pick. In general, if you're working on the design, choose hierarchical for easy, graphical access, so that the end result can be transformed into a subcircuit that's ready to be encrypted, if you so desire.
As a subcircuit, I'd have access to the Components Attribute Editor and a few more fields for setting up parameters as opposed to the single PARAMS line that the hierarchical block uses
Those fields mean nothing in terms of netlist, and the names shown in the component attribute editor are also flattened: if you check the netlist, all the lines get cropped up into a single line that belongs to the subcircuit.
They are only meaningful as some combinations, in terms of the order in which they appear in that line, and which has differnent effects together with the symbol: in some cases, it's possible to prevent the symbol from being edited. See, for example, an opamp from the existing library and try R-Click
, with or without Ctrl
-- it will not let you. This goes hand-in-hand with the encryption of subcircuits, but not hierarchical designs.
Best Answer
Besides @Voltage Spike's answer, a warm recommendation would be to avoid conditionals in behavioural expressions like
if()
,buf()
, etc (or other discontinuous functions likelimit()
,uramp()
, etc), because the solver might get stuck with "timestep too small". They might work, they might not, they could be attempted to be "tamed" with some strategically placed small capacitors to help out the sharp transitions, but there already is a very convergent-friendly solution: A-devices.For your case, you can replace these:
B2
and the one for the second term inB3
with[Digital]/inv
B3
andB7
with[Digital]/and
B4
,B6
, andB8
with either[Digital]/schmitt
(ordiffschmitt
) withvt=<...> vh=0
, or with[Digital]/buf
withref=<...>
B7
with[Digital]/schmitt
withvt=0 vh=0
, or withbuf1
withref=0
For the cases where you need to use a voltage, it's simple, just add the respective node to the input of the logic gate. For currents, since you're only using
I(L1)
, you can add an H-source withL1 1
as value (which might be a better choice than a B-source).And, while we're at it:
ZCD
both the node for the Q output ofA2
and the output ofB4
. Since you are using a behavioural voltage source, it can't be intentionalB6
with a normal voltage source. I only see it used inB7
, so you can just delete the source altogether and use aninv
withref=1
R1
andR[6,7,8,9]
, they're not needed. The A-devices have a default output resistance of 1 Ω (one exception, not needed here), so adding a resistor will change the output levelsC1
is useless there since voltage sources have zero internal resistance. You could add a seris resistance between the source and the cap, but you'd be better off addingRser
to the source, in which caseC1
can be safely deleted andCpar
can be specified in the source..model d d ron=10m roff=10meg vfwd=0.7 epsilon=0.1 revepsilon=50m
will do just fine.On the bright side, the VCSW have their
.model
cards with a negative hysteresis and very acceptable range between the ON/OFF states, so that's a bravo from me.With these, here's a quick remake:
And the
.asc
file, where I have only usedtd
for thesrflop
; feel free to addtau
andtripdt
, they will only help: