Electronic – Using both edges of a clock

fpgaintel-fpgaverilog

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here is a snippet of my code:

  always @(posedge low_jitter_clock_i or negedge low_jitter_clock_i or posedge reset_i) begin
    if(reset_i) begin
      fixed_clock <= 1'b0;
      divider_dummy <= 'b0;
    end else begin
      fixed_clock <= fixed_clock_next;
      divider_dummy <= divider_dummy_next;
    end
  end

Now when I compile this, Quartus II throws the following error:

Verilog HDL Always Construct error at adc_clocking.v(83): event
control cannot test for both positive and negative edges of variable
"low_jitter_clock_i"

How can I use both the positive and negative edge of a given clock in my design?

Best Answer

When you assign to a register in an edge-sensitive always block, you're defining a flip-flop. FPGAs do not have flip-flops that can trigger on both edges of a clock.

In order to do what you want, you are going to need to have two separate always blocks, one for each edge of the clock, and then figure out a way to combine the outputs of the two blocks without creating glitches.

For example, one always block could contain your programmable divider. Design it so that the output duty cycle is less than 50% when given an odd number. Use the second always block (on the other clock edge) to delay the output of the first block by 1/2 clock, then OR the two outputs together. Disable the output of the second block for even divider values.

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