Electronic – Using two NPN transistors to form an AND gate


I'm a little puzzled by this schematic and am wondering if this is correct?
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When I wire this up with 2N222 transistors and supply 5V at VCC with all 10K ohm resistors, and A and B are GND, the meter measurement at OUT is 0. If A and B are VCC, then OUT is close to VCC. All good. Now if B is GND, while A is VCC, OUT is GND, also good. However, when A is GND and B is VCC, I see approx 2V at OUT. I was expecting GND. Is this because the collector on the bottom transistor does not have any voltage and current is flowing from the base to the emitter? If so, is this schematic incorrect for an AND gate?

Best Answer

OK, definitely seems like they're a lot of schematics on the net that shows an AND gate as I posted originally that are wrong. The following schematic appears to work perfectly for me which I found on a youtube video on constructing an AND gate using transistors.

enter image description here