Electronic – Using Webpack from the command line, but without a project file

fpgasynthesisvhdlxilinx

I recently got Webpack to sorta work for me on my Linux system… but I tried using ISim for simulation of my designs and got hit by a problem. And from what I can tell, this problem isn't Xilinx's problem, since I'm not using a supported OS(Arch Linux)… and I can't figure out how to fix it… so I'm going to do something that hopefully is easier in the long run.

Anyway, I want to use ghdl/gtkwave for simulation, and then use Webpack's tools only for when I need to generate a bitstream for uploading to my FPGA… And I want it all to be run easily from a makefile. Of all the makefiles I've seen for using their command line tools though, they all require a project file. I'd really rather just specify files manually somehow in my makefile. I'd rather not have to, every time I add a file, change the project and my makefile. Is this possible?

Best Answer

Not that I am aware. Another approach is to use a script instead of a makefile. The script can then create the project file so you do not to manually edit multiple files.

You can use TCL to drive the ISE tools. The ISE tools will generate example code for you. More information on using TCL can be found here, http://devbisme.webfactional.com/blogs/devbisme/2012/04/03/running-weeds

If you want a Python option for building Xilinx ISE projects, see Guenter Dannoritzer's Python scripts, which generate the underling tcl, but the OO interface in Python is better than generating tcl directly, http://www.myhdl.org/doku.php/projects:ise_py. I have made some updates to the scripts here, https://bitbucket.org/cfelton/examples/src/tip/tools

An example, you can quickly and as easily create an ISE project.

# set up pin configuration for the FPGA
fpga = Fpga(path=ppath)
fpga.setPin('clk', 'P124')
fpga.setPin('srst', 'P8')
fpga.setPin('led<0>', 'P92')
fpga.setPin('led<1>', 'P93')
fpga.setPin('led<2>', 'P95')
fpga.setPin('led<3>', 'P96')
fpga.setPin('led<4>', 'P97')
fpga.setPin('led<5>', 'P98')
fpga.setPin('led<6>', 'P99')
fpga.setPin('led<7>', 'P100')
fpga.setDevice('spartan3', 'xc3s400', 'tq144', '-5')

imp = Xilinx(ppath, 'stroby')

imp.setFpga(fpga)
imp.addHdl((vfile))
imp.createTcl() 
imp.run()

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Electronic – Generating a MSS file at command-line

You can use the Xilinx tool appguru to generate an MSS file from the exported XML file

appguru -hw proc.xml -app empty_application

See appguru -h for help

Electronic – VHDL: Architecture naming and interpretation

Looking at an entity, how can one determine the actual architectural model being used without hints from the architecture name?

You can't - when it is instantiated or configured the architecture can be specified (if there is more than one to choose from) or a default will be chosen for you.

If specifying multiple architectures for a single entity (which I understand is possible) do you simply give the architectures different names in the same file or...?

You give them different names. It doesn't have to be within the same file (in fact VHDL cares a lot less than you might think about what's in what file)

Are the architecture names confined to a given entity (that is, is there any problem with "namespaces" by using the same architecture name over multiple entities)?

They are "attached" to an entity, so can be reused.

I often use a1 as my architecture for everything synthesisable as

rtl implies lower level (to many readers) than I write at.
behavioural often implies non-synthesisable (to some readers)
synth is used by the synthesiser for it's model (otherwise I'd have used that)

a1 has been non-conflicted so far and doesn't cause confusion ;)

If I actually have more than one architecture, I tend to name them verbosely (for example hard_multipliers and lut_multipliers for a filter which instantiates - or not - MUL18 blocks).

Very often you only have one architecture, so it doesn't matter. Good entity names are much more important.

It seems there is a distinction between RTL and behavioral, but as mentioned above I'm not really seeing it in the examples I've seen (often I only see one architecture being defined). Is one architecture more common than the others?

It's historical - you didn't used to be able to synthesise "behavioural" code (which at one point included things like adding!) - so you created an RTL version which instantiated adders and the like. (That's as I understand it - I've been writing behavioural (and yet still synthesisable) code since I started VHDLing in about 1999!)

Best Answer

Related Solutions

Electronic – Generating a MSS file at command-line

Electronic – VHDL: Architecture naming and interpretation

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