Electronic – VCC trace routing on a two-layer board with TQFP chip


I'm just trying to layout a PCB with CY7C68013A (100-pin TQFP) on it. It's a sort of experiment, so I'd like to use 2-layer PCB, 4 layer PCBs are just too expensive. This leads to some interesting layout issues (note, that I'm more concerned with signal integrity than EMI).

I decided to use bottom layer as a ground plane, yet I have a really hard time choosing the best way to route the VCC trace. There are a few high-speed signals routed from the left and bottom edges of the chip to the connector on the left side of the board (carrying up to ~30MHz signals). There are 3 VCC/GND pairs on the left side, and 3 more on the bottom of the chip, to make things complex – I need to route VCC away from between those fast signals..

This makes it necessary to either:

a) route parts of these signals on the bottom layer and keep most VCC on top

b) route these signals on top of the board and route some segments of VCC on the bottom layer (but this introduces holes in the bottom layer's ground plane, exactly underneath the signal traces, making the return path's loop bigger)

Any advice? Is it OK to route the VCC underneath the chip on the bottom layer?
This would let me leave the ground solid under my fast signals.

How about top layer? (this would require a power track connected to the pin from one side, and decoupling capacitor stub track from the other side – that doesn't sound good to me).

Perhaps I'm overestimating the potential issues, but it's interesting problem on its own – I can imagine many projects choosing 2-layer PCBs to lower the costs.

Best Answer

That's the Cypress FX2LP USB microcontroller (I recognize it because I use it myself). If you're using the Hi-Speed USB transceiver, then you should really go with a 4-layer board. Without that ground plane right below the top layer, it will be near impossible to get the 90 ohm differential impedance that you want for the USB D+/D- lines.

http://www.cypress.com/?id=4&rID=34128 flat out states that 4 layers is required. It also states that controlled impedance is required, but in my experience you can usually get away without it, so long as you carefully research your fab's typical stack-up and work out the right width, space, and height.

http://www.cypress.com/?docID=25406 also provides more info on calculating the width, space, and height for the D+ and D- lines.

4-layers isn't that much more expensive; Advanced Circuits has a 66 each deal for 4 layer boards that I use quite often for projects that use that very chip, as opposed to the 33 each deal for 2 layers.

In regards to your actual question...use plenty of bypass caps, as close to the pins as possible. If you split the bottom layer to have VCC and GND, don't have a trace cross the split on the top layer. Keep all high-speed signals on the top layer because the via inductance can kill what fragile signal integrity a 2-layer board has.