Electronic – Verilog – Can you `define a bit slice

You've got the order wrong. When using module-instance parameter value assignment (the rather wordy terminology for this method), the syntax is:

module-name #(parameter-assignment) instance-name (module-terminal-list) ;

where the parameter assignment can be by name or by the order of the values. You're already familiar with the module terminal list, so I'll just give the parameter BNF:

parameter-assignment ::= (values-by-name / values-by-order) 
values-by-name ::= .parameter-name(parameter-value)*[, parameter-name(parameter-value)]
values-by-order ::= parameter-value*[, parameter-value]

So your example should be one of the following:

add #(.wd(8)) len_plus_1(.a(len),.b(8'h1),.o(lenPlus1));
add #(8) len_plus_1(.a(len),.b(8'h1),.o(lenPlus1));

The former (named) version is preferred, because it maintains its behavior if you add another parameter.

The following example gives additional options (this is adapted from Figure 9-4 in Verilog HDL: A Guide to Digital Design and Synthesis by Palnitkar)

module bus_master;
  // Note: These could also be ANSI C-style parameter declarations with 
  // module bus_master (#parameter delay1 = 2, delay2 = 3, delay3 = 7);
  parameter delay1 = 2;
  parameter delay2 = 3;
  parameter delay3 = 7;
  ...
  <module internals>
  ...
endmodule

module top;
  // Assignment by name:
  bus_master #(.delay2(4), delay3(8)) b1();
     //delay1 = 2 (default), delay2 = 4, delay3 = 8
  bus_master #(.delay1(1), delay3(6)) b2();
     //delay1 = 1, delay2 = 3 (default), delay3 = 6

  // Assignment by order:
  bus_master #(7, 8, 9) b3();
     //delay1 = 7, delay2 = 8, delay3 = 9
  bus_master #(1, 3, 5) b4();
     //delay1 = 1, delay2 = 3 (default, but by assignment), delay3 = 5
  bus_master #(1, 5) b5();
     //delay1 = 1, delay2 = 5, delay3 = 7 (default)
endmodule

There is also another method which uses the defparam keyword to define the values before instantiation like this:

module top; 
  defparam b6.delay1 = 1;
  bus_master b6();
     //delay1 = 1, delay2 = 3 (default), delay3 = 7 (default)
endmodule;

but that's considered poor style (though personally, I'd prefer it to the values-by-order syntax).

You probably do want something like the circuit shown by clabacchio.

This is easily rendered in Verilog as

reg [4:0] d;
always @(posedge clk) begin
    d <= { d[3:0], d[4] ^ d[2] };
end

This is, as others mentioned, a linear feedback shift register, or LFSR, and it generates the maximal length pseudo-random bit sequence that can be produced with a 5-bit state machine. The state machine traverses 31 states (\$2^n-1\$, where n is the number of registers) before repeating itself.

Of all the states that can be encoded by 5 registers, only one is not used, which is the all-0's state. The all-0's state is a lock-up state --- if the state machine gets into that state by an error, it will be stuck permanently in the all-0's state, as you can see because 0 ^ 0 = 0. This means you have to be sure (using a synthesis directive in the Verilog or constraints file) that the registers don't initialize to the all-0's state.

If you need the all-0's state not to lock up, you can use an XNOR in place of the XOR gate, and get a sequence that includes the all-0's state and locks up in the all-1's state.

Also be aware that the longest run of 1's produced by this state machine is 5 in a row, and the longest run of 0's is 4 in a row. This can be important if you are using the PRBS to test a system with ac-coupling...longer runs will stress the system more.

In communications testing, longer sequences are more common, mainly to exercise more of the low frequency behavior of the system:

PRBS7

reg [6:0] d;
always @(posedge clk) begin
    d <= { d[5:0], d[6] ^ d[5] };
end

PRBS23

reg [22:0] d;
always @(posedge clk) begin
    d <= { d[22:0], d[22] ^ d[17] };
end

PRBS31

reg [30:0] d;
always @(posedge clk) begin
    d <= { d[30:0], d[30] ^ d[27] };
end

Notice that it is not always the final two registers that are "tapped" to generate the incoming bit of the shift register.

Xilinx app note XAPP052 gives a handy table of connections to be used to generate any size PRBS from 3 to 168 registers.

App note XAPP211 shows how to implement them efficiently in Xilinx devices. Essentially, a single look-up table in a single logic block can be used to implement up to 32 registers worth of shift register (depending on architecture).

LFSRs can also be used to implement a counter efficiently if you don't care about the intervening states, just how long takes to count down to some terminal value.