Electronic – Verilog modules: estimating power consumption before physical design

cpudigital-logicpowerverilog

What can a designer do to get an idea of how much power a various module with consume? It seems like there should exist some decent heuristics to go about doing this, else we would have to wait until deeper into the physical design stage.

A basic idea might be some linear combination of regs + gates + wires, like say:

P = x*numRegs + y1*numANDgates + y2*numORgates + ... + z*numWires 

And perhaps the coefficients could come from a standard cell library. Which unfortunately I don't know where to find, for free at least.

Really though, I just want to be able to do back-of-the-napkin calculations to compare similar modules to each other. Any suggestions?
EDIT – by all means, share any free CAD tools that may help =)

Thanks

Best Answer

You can probably estimate static/leakage power consumed using a formula like you have mentioned. The other aspect is the power consumed while switching which would require some sort of stimulus to measure.

I have used power compiler for one of previous my class projects, which requires the switching activity information which is dumped by a simulator.

http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/power/power_compiler_rtl.gif