Electronic – Verilog register output: reg or wire

registerverilog

If I want to model a simple register I would expect to have an internal 'reg' element to hold the value and I would connect this with a 'wire' output. The reg drives an internal output.

However, I've looked up several examples and most use an output of type 'reg'. I don't understand why you would do that. Aren't you storing the value in two places this way? Is there a difference in behavior?

Best Answer

The way to choose how to declare your signal is not by how it will be physically instantiated, but by how you will syntactically assign its value.

If the signal is driven by assignments in a procedural block (a block beginning with always or initial), then it must be declared as reg.

If the signal is driven by continuous assignment (an assign statement) or is the output of a module instance, then it must be declared as wire (or one of its variants like wor or wand), or as an output without the reg qualifier.

A reg signal might be physically the output of either a latch or a flip-flop or of combinatorial logic (for example, there's a very common way of inferring a combinatorial multiplexer using an always block). A wire might be physically the output of a latch or a flip-flop or combinatorial logic (for example if the flip-flop is within a submodule).

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Electronic – Verilog UART Transmitter Sends Bytes Out of Order

The problem is that your "transmission_test" code is written such that it assumes that "is_transmitting" from the UART goes true before the clock edge that follows the assertion of "begin_transmit". It doesn't -- it takes a clock cycle before the UART transmitter moves out of its "idle" state, after which "is_transmitting" is true.

As a result, your "transmission_test" state machine is advancing two states for each byte transmitted, and you see only every other byte at the output of the UART.

There are many minor problems with your code samples, but the main thing you need to fix is to verify that "is_transmitting" has gone true before you advance to the next byte in the message.

This would have been pretty obvious if you had taken the time to simulate this project. I can't overemphasize the importance of simulation in verifying FPGA code. Take the time to get familiar with your simulator and learn how to write good module testbenches.

Electronic – How to wire output buses together

Purely answering how to create a parametrised width zero. hopefully another answer can cover the best practise for multiple drivers.

localparam DATA_W = 8;
i = {8{'1b0}} ;

i = 'b0 ; //RHS width is matched to LHS, early version limited to 32bits

i = '0;  //Introduced in 2012 SystemVerilog simplest way to x every bit : 'x

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Related Solutions

Electronic – Verilog UART Transmitter Sends Bytes Out of Order

Electronic – How to wire output buses together

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