Electronic – VHDL: Can’t give a std_logic type a value of 0 or 1 (on or off)

vhdl

I have the following code from one of the files in a project:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

entity twoplayermux1 is
    port
    (
        --inputs:
        show                 :  in std_logic;
        set              : in std_logic;
        input                : in std_logic_vector(7 downto 0);
        try                  : in std_logic;
        player               : in std_logic;

        --outputs:
        show_out             : out std_logic;
        set_out          : out std_logic;
        input_out        : out std_logic_vector(7 downto 0);
        try_out          : out std_logic;

        show_out2        : out std_logic;
        set_out2             : out std_logic;
        input_out2       : out std_logic_vector(7 downto 0);
        try_out2             : out std_logic
    );
end twoplayermux1;

architecture Behavioral of twoplayermux1 is
begin

process (show,set,input,try,player)

begin

case(player) is
        when "0" =>
            show_out <= show;           
            set_out <= set;
            input_out <= input;
            try_out <= try;
        when "1" =>
            show_out2 <= show;          
            set_out2 <= set;
            input_out2 <= input;
            try_out2 <= try;
        when others =>
            null;
        end case;

    end process twoplayermux1;

end Behavioral;

However, because player is an std_logic, the compiler gives me the following error:

Error (10515): VHDL type mismatch error at TwoPlayerMux1.vhd(36): std_logic type does not match string literal

The error is in the case statement where I wrote when "0" => and when "1" =>.
If I change playerto an std_logic_vector of 2 bytes and write when "00" => or when "01" => then it is being compiled without any errors. However, I do not want a std_logic_vector of 2 bytes. It needs to be 1 byte like so: player : in std_logic_vector(1 to 1); , but that doesn't work either.

NOTE:

It is a project for an FPGA board.

Best Answer

You have to options:

  1. Use when '0' , with player as std_logic
  2. Use when "0", with player as std_logic_vector(0 downto 0)