VHDL – Clock Divider Problem

testbenchvhdl

I have a 100 Mhz clock and I need a 0.5 Khz clock. So I wrote this code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clkdiv is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           clkout : out STD_LOGIC);
end clkdiv;

architecture Behavioral of clkdiv is
signal temporal : std_logic := '0';
signal counter : integer range 0 to 99999 := 0;
begin
process (reset, clk) begin
if (reset = '1') then
       temporal <= '0';
       counter  <= 0;
elsif rising_edge(clk) then
    if (counter = 99999) then
        temporal <= not temporal;    
        counter <= 0;
    else
        counter <= counter + 1;
    end if;
end if;
end process;
clkout <= temporal;

end Behavioral;

And testbench for it:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;



entity testbench is
    
end testbench;

architecture Behavioral of testbench is
component clkdiv
Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           clkout : out STD_LOGIC);
           end component;
 
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal clkout : std_logic;
constant clk_in_t : time := 10 ns;
        
begin
uut : clkdiv port map (
    clk => clk,
    reset => reset,
    clkout => clkout);
    
    process
    begin
    clk <= '0';
    wait for clk_in_t / 2;
    clk <= '1';
    wait for clk_in_t / 2;
    end process;
    
process
    begin
    reset <='1';
    wait for 100 ns;
    reset <= '0';
    wait;
    end process;
end;

However, testbench results are like that:

Can anyone tell me what's wrong? Thank you all.

Best Answer

I've rounded up all the good advice from the comments into an answer.

Clock Strobe

Generates a slower strobe from a faster clock.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ClockStrobe is
    generic
    (
        CLOCK_PERIOD : time := 20 ns;
        STROBE_PERIOD: time := 2 ms
    );
    port
    (
        reset : in std_logic;
        clock : in std_logic;
        strobe: out std_logic
    );
end entity;

architecture V1 of ClockStrobe is

    constant MAX_COUNT: natural := STROBE_PERIOD / CLOCK_PERIOD - 1;
    signal counter: natural range 0 to MAX_COUNT := 0;  -- Specify the range to reduce number of bits that are synthesised.

begin

    process(all)
    begin
        if reset then
            strobe <= '0';
            counter <= 0;
        elsif rising_edge(clock) then
            if counter = MAX_COUNT then
                strobe <= '1';
                counter <= 0;
            else
                strobe <= '0';
                counter <= counter + 1;
            end if;
        end if;
    end process;

end architecture;

Test Bench

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity ClockStrobe_TB is
end;

architecture V1 of ClockStrobe_TB is

    constant clock_period : time := 10 ns;
    constant STROBE_PERIOD: time := 2 ms;
    -- constant CLOCK_PERIOD : time := 10 ns;
    -- constant STROBE_PERIOD: time := 40 ns;

    signal halt_sys_clock: boolean := false;

    signal reset: std_logic := '0';
    signal clock: std_logic := '0';
    signal strobe: std_logic;

    component ClockStrobe is
        generic
        (
            CLOCK_PERIOD : time := 20 ns;
            STROBE_PERIOD: time := 2 ms
        );
        port
        (
            reset : in std_logic;
            clock : in std_logic;
            strobe: out std_logic
        );
    end component;

begin

    ClockGenerator:
    process
    begin
        while not halt_sys_clock loop
            clock <= not clock;
            wait for CLOCK_PERIOD / 2.0;
        end loop;
        wait;
    end process ClockGenerator;

    Stimulus:
    process
    begin
        -- Do reset.
        wait for CLOCK_PERIOD / 4;
        reset <= '1';
        wait for CLOCK_PERIOD / 2;
        reset <= '0';

        -- Wait for a couple of strobes.
        wait for 2.1 * STROBE_PERIOD;

        -- Halt simulation.
        halt_sys_clock <= true;
        wait;
    end process;

    CS:
        ClockStrobe
        generic map
        (
            CLOCK_PERIOD => CLOCK_PERIOD,
            STROBE_PERIOD => STROBE_PERIOD
        )
        port map
        (
            reset => reset,
            clock => clock,
            strobe => strobe
        );

end architecture;

Simulation Results

Figure 1 – Clock strobe simulation results: 100 MHz clock; 500 Hz strobe.

Using the Clock Strobe

And here is how to use the clock strobe for slow logic.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SlowLogic is
    port
    (
        reset : in std_logic;
        clock : in std_logic;
        strobe: in std_logic
        -- Slow inputs and outputs here.
    );
end entity;

architecture V1 of SlowLogic is

begin

    process(all)
    begin
        if reset then
            -- Reset slow outputs, etc.
        elsif rising_edge(clock) then
            if strobe then
                -- Do slow logic on inputs and outputs.
            end if;
        end if;
    end process;

end architecture;

Related Solutions

Electronic – Clock divider VHDL

Your code works if you init DVSR to 50000 instead of 5000000. It will generate a pulse every 1ms with a width of clk period, this will be 0.000...01% high and 99.99..99% low To generate a clock with 50% high 50% low I would do the following.

library ieee;
use ieee.std_logic_1164.all;

entity clock_divider is

  generic (
    divider : positive := 50000);       -- for 1 ms tick at 50mhz clk input

  port (
    reset, clk : in  std_logic;         -- reset and clock in
    out_red    : out std_logic);        -- Reduced freq clock out
end entity clock_divider;

architecture implementation of clock_divider is
 signal ClockDiv : natural range 0 to divider/2 := 0;    -- clock divide counter
 signal clk_out  : std_logic;
begin  -- architecture implementation

 clock_div_p : process (clk, reset) is

 begin  -- process clock_div_p
   if reset = '1' then                 -- asynchronous reset (active high)
     ClockDiv <= 0;
     clk_out  <= '0';
   elsif clk'event and clk = '1' then  -- rising clock edge
     if (ClockDiv = divider/2) then    -- switch polarity every half period
       ClockDiv <= 0;
       clk_out  <= not clk_out;
     else
       ClockDiv <= ClockDiv +1;
       clk_out  <= clk_out;
     end if;
   end if;
 end process clock_div_p;

 out_red <= clk_out;

end architecture implementation;

Electronic – Why is the simple counter VHDL not working? Where did the signals go

the rising_edge() parameter is only really for clock signals. One option would be the following:

clk_proc: process( clk, switch1, switch0 )
begin
    if switch1 = '1' then
        counter <= ( others => '0' );
    elseif rising_edge( clk ) then
        if switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

clk_proc: process( clk, switch1, switch0 )
begin
    if rising_edge( clk ) then
        if switch1 = '1' then
            counter <= ( others => '0' );
        elsif switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a lot easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.