Electronic – VHDL constant range declaration

fpgavhdl

I have a bunch of network packets and I am trying to specify fields in them, something like

constant UPPER_BOUND : natural := 15;
constant LOWER_BOUND : natural := 7;

I know that this syntax is CORRECT

The range does not change throughout the application and I was thinking if it is possible in the VHDL syntax to declare a constant range if you will. Something to the effect of:

constant FIELD_RANG : natural range := (15 downto 7);

I know that this syntax is WRONG

But, I was trying to understand, if specifying a generic range is possible ? Is the 1st mentioned syntax the only way to do this ?

Best Answer

I think the second line should be

constant LOWER_BOUND : natural := 7;

above. (OK, it is now! :-) But anyway... welcome to a language with a proper type system! Learn to use it, and you will love it. Or learn to fight it, and you will hate it. Your choice...

What you are looking for is either

type Field_Range is range UPPER_BOUND downto LOWER_BOUND;

subtype Field_Range is Natural range UPPER_BOUND downto LOWER_BOUND;

according to whether you want type safety, or easy mixing of Field_Range with other integer quantities.

Either way you can say

Field : Array(Field_Range) of Something;

for i in Field_Range loop
   ...
end loop

and (almost!) never worry about bounds errors again.

What is the difference between Type and Subtype? That'll take a little learning, but here's a start:

if you have the following,

constant N : Natural := 7;
constant F : Field_Range := N;

the subtype will allow it, the new type will not, you would need to convert:

constant F : Field_Range := Field_Range(N);

Related Solutions

Electronic – VHDL functions with generic or “run time variable”, synthesis issues

Synthesis tools work very hard to evaluate everything at compile time that they possibly can. For everything else, they synthesize logic -- including function calls, assuming that the function is synthesizable (some are not).

Therefore, the answer to your question is, "it depends". It doesn't matter if the actual parameter to the function is a generic or a signal (port) -- if the value is known at compile time, the synthesis tool will evaluate the function at compile time and use the result. The only difference is that a generic is by definition known at compile time, while a signal may or may not be.

If the function needs to be evaluated at run time, then the synthesis tool will generate the logic required to do that, assuming that no non-synthesizable constructs have been used in the body of the function.

Electronic – VHDL if generate in the preamble, is it possible

You can't put statements in (formally there is no "preamble" so) the declarative region.

However you can wrap statements and their associated declarations in a block statement. This keeps the declarations and their statements closely scoped together, avoiding bugs where statements are associated with the wrong declarations (which would be possible in your example.

So do that :

architecture arch of my_entity is
-- declarative region

begin
-- concurrent statement region

   flag_true : if flag /= 0 generate
      -- a block statement
      true_block : block
         constant K1 : integer := 32;
      begin
         y(K1 - 1 downto 0) <= not x(K1 - 1 downto 0);
      end;
   end generate flag_true;

end architecture arch;

And an observation :

if /=0 means true there is probably something very wrong with the design : you have true booleans in VHDL, you don't have to obscure the meaning so you can do everything with an integer. Then you can write

if flag generate ...

Best Answer

Related Solutions

Electronic – VHDL functions with generic or “run time variable”, synthesis issues

Electronic – VHDL if generate in the preamble, is it possible

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