Electronic – VHDL D-type asynch flip flop

digital-logicvhdl

I just started learning vhdl code and i wrote this code for a D type asynch flip flop. How should i modify my code so that it has a second D-type, with the input to the second being fed from the output of the first?.

library ieee;
use ieee.std_logic_1164.all;

entity FLIPFLOP is
port ( 
  clk : in  std_logic ;
  clr : in  std_logic ;
  D   : in  std_logic ;
  Q   : out  std_logic
  );
end FLIPFLOP;

architecture behav of FLIPFLOP is
begin
process (clk,clr,D)
begin
if clr = '1' then
Q<= '0';
elsif rising_edge (clk) then
Q<= D;
end if;
end process;
end behav;

Best Answer

I like to keep shift registers defined as vectors. Doing so helps maintain code in the long run. You'll find that this is only 2 lines longer than what you already had (ie. one line for std_logic_vector declaration, and another line to assign the output).

Try this:

entity dualff is
port (
    clk : in  std_logic;
    clr : in  std_logic;
    d   : in  std_logic;
    q   : out std_logic );
end dualff;

architecture Behavioral of dualff is
    signal dffs : std_logic_vector (1 downto 0) := b"00";
begin
    q <= dffs(1);
    process (clk, clr)
    begin
        if clr = '1' then
            dffs <= "00";
        elsif rising_edge (clk) then
            dffs <= dffs(0) & d;
        end if;
    end process;
end Behavioral;

RTL: RTL

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