Is it true that one can pass boolean, integer and its subtypes as well as std_logic_vectors as generic to a VHDL entity?
Does this list also include enum types, which is user defined i.e describe an enum in package and then include it in the entity declaration and then declare a generic of that enum type?
Best Answer
Yes, yes, yes and yes :).
See for example our PoC.io.uart.fifo module:
This module wraps a transmitter and receiver plus bit-clock generator in a single module and attaches two FIFOs. The module makes extensive use of generics in form of:
The latter one is defined in the package
PoC.uart
, which is referenced by ause
clause. The top-level module, that instantiatesuart_fifo
, needs also to reference this package.