Electronic – VHDL don’t care for integer

best practicevhdl

I am writing a reset for a vhdl statemachine that has an integer signal, which is initialized in the second state of the statemachine. However for completeness (assign every signal to avoid latches) I would like to assign a don't care value to the signal, so the synthesis tool has the most room for optimization.

Is there any way to assign a don't care value to a signal of the type integer?
(I know I could convert it to signed/unsigned and assign (others => '-' ) however it feels more natural to write this code with integer, since this allows to write if var=3 ... instead of if to_integer(var)=3 ... or if var=to_(un)signed(3, var'Length)... which feels uncomfortable.

Of I can not assign don't care, what is the best practice, assign the value, that I will assign in the second state, leave it unassigned or others? (I would go with assigning the value from the second state early)

Best Answer

There is no "don't care" for integer; if you are modelling digital logic with X, Z, don't care etc, then numeric_std.signed/unsigned is the right way to go.

But look at the numeric_std package more carefully; most operators including = are overloaded with forms that allow mixing [un]signed and integer freely, so that if my_unsigned_var = 3 just works...

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Electronic – VHDL increase decrease integer value

Your code doesn't compile, you can't use <= to assign to a variable. Nor can you assign to an input (which counter is defined as...)

You also can't have two separate processes writing to the same signal (when it's of a non-resolved type, like integer). Is this an academic exercise? Why not just have a single process which does:

if rising_edge(clk) then
  if up = '1' then
     count <= count + 1;
  elsif down = '1' then 
     count <= count - 1;
  end if;
end if;

As you have a limited range counter, you'll have to be explicit about making it wrap around (or saturate) when you try and increment it or decrement it beyond the acceptable range. The simulator will die otherwise. The synthesis tool may or may not do what you require, depending - but it's better to be explicit with that sort of behaviour.

Also, get rid of std_logic_arith - if you want vectors to be treated as numbers, use ieee.numeric_std.all instead

Electronic – VHDL logical operation on integer

A better way than using std_logic_vector and the non-standard std_logic_arith and std_logic_signed libraries is to use IEEE.numeric_std.all; and make the counter unsigned (or signed in other contexts where you need negative values).

signal hcount  : unsigned(7 downto 0);

And you can perform conversions to and from integer, and bitwise operations:

hcount <= to_unsigned(123,hcount'length);

signal somereg : std_logic_vector(7 downto 0);
...
somereg(to_integer(hcount(2 downto 0)) <= <a bit value>;

However in the given example, the bitwise operations turn out to be unnecessary: instead of masking bits to extract a 3-bit register address, you could use division and mod operations. Synthesis tools (mostly) aren't stupid : divide and mod by powers of 2 are optimised into the obvious field extractions and don't even generate "and" gates.

signal hcount    : natural range 0 to 235;
signal reg_addr  : natural range 0 to 7;

signal somereg : std_logic_vector(7 downto 0);
...
reg_addr <= hcount mod 8;
somereg(reg_addr) <= <a bit value>;

One benefit of this (apart from fewer ugly type conversions) is that you still profit from the integer subtype you declared for hcount : incrementing it to 236 will raise an overflow error in simulation, allowing you to catch and correct logic errors early.

Best Answer

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