Electronic – VHDL increase decrease integer value

vhdl

I have create project witch has an "counter" counter = Integer. I need to increase/decrease an integer value by pressing the buttons. the progress has 2 entitys, entity 1 should increase
the value and entity 2 should decrease the value, Im not allow to do so with component how to do this?

-- component 1 -------------------------------
entity MyCounter is
 port(
    clock: in std_logic;
    KEY: in std_logic;
    counter: in integer range 0 to 15;
    clk_out: out std_logic
  );
end MyCounter; 

architecture arch of MyCounter is

component decrease
    port(

    clock: in std_logic;
    KEY: in std_logic;
    counter: in integer range 0 to 15;
    clk_out: out std_logic

        );
end component;

begin
    p1: process(clock, KEY)
     variable counter : integer;
       begin
         if KEY = '1' then
          counter <= counter + 1;
         end if;
end process; 

end arch;


-- component 2 -------------------------------
entity decrease is
 port(
    clock: in std_logic;
    KEY: in std_logic;
    counter: in integer range 0 to 15;
    clk_out: out std_logic
  );
end decrease ; 

architecture arch of decrease is
begin

    p1: process(clock, KEY)
     begin
      if KEY = '1' then
        counter <= counter - 1;
    end if;
end process; 

end arch;

Best Answer

Your code doesn't compile, you can't use <= to assign to a variable. Nor can you assign to an input (which counter is defined as...)

You also can't have two separate processes writing to the same signal (when it's of a non-resolved type, like integer). Is this an academic exercise? Why not just have a single process which does:

if rising_edge(clk) then
  if up = '1' then
     count <= count + 1;
  elsif down = '1' then 
     count <= count - 1;
  end if;
end if;

As you have a limited range counter, you'll have to be explicit about making it wrap around (or saturate) when you try and increment it or decrement it beyond the acceptable range. The simulator will die otherwise. The synthesis tool may or may not do what you require, depending - but it's better to be explicit with that sort of behaviour.

Also, get rid of std_logic_arith - if you want vectors to be treated as numbers, use ieee.numeric_std.all instead

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