Electronic – VHDL – passing through INOUT ports

fpgavhdl

If I need to wrap an existing, previously top-level VHDL design for an FPGA with INOUT ports in another new top-level entity… what's the proper way to pass through PART of an INOUT port?

Usually, I'd just remove the INOUT from the non-top layer and replace it with directional ports… but my client wants to keep that code entirely unchanged (so the HDL supports two different board designs).

Say entity old_top_level has a port SPARE_IO : INOUT std_logic_vector(7 downto 0). Another entity new_top_level has SPARE_IO_WRAPPED : INOUT std_logic_vector(7 downto 0).

I need to redirect a single element of SPARE_IO.

Will the following work (defined in the body of new_top_level):

SPARE_IO_WRAPPED(6 downto 0) <= SPARE_IO(6 downto 0);
SPARE_IO(6 downto 0) <= SPARE_IO_WRAPPED(6 downto 0);
SPARE_IO(7) <= SOMETHING_ELSE;

It seems to compile, but that's not saying much.

EDIT I edited to clarify the INOUT signal isn't completely passed through so I can't just use the PORT MAP.

Best Answer

Inouts can exist internally or externally. Indeed in reality they don't exist as physical gates, in both cases they are two gates in oposite directions in parallel.

Internally inout is usually imlememnted as an array of OR gates for the driver and multipel connections to AND gates for the receivers. There is no tristate internally.

Externally inout is usually two gates, the output one being able to be tristated by some common select signal.

VHDL does not care about 'internal' or 'external' signals.

So long as the VHDL syntax inferrs some means of deciding which device is being selected for access to the inout, the same code can be used as a top level or lower level module.
e.g. Within your module(s)

bus<=myoutdata when RD='1' else (others=>'Z');
myindata<=bus;

The else others bit suggests to VHDL that the bus is shared if bus is an inout. The shard signal, a version of which must go to every module that has access to the bus arbitrates who has access.

Related Solutions

Electronic – Problem getting VHDL syntax correct

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.

Electronic – Get_ports vs Get_pins vs Get_nets vs Get_registers

I/Os of the top-level block are called port, I/Os of the subblocks are called pin. So get_ports and get_pins commands must be used accordingly.

If the main clock is an input of the top-level block, get_ports is the appropriate command. For example:

create_clock -name CLK [get_ports clock_main] ...

Since clock_1 and clock_2 are the inputs of the subblocks, get_pins must be used in this case.

create_clock -name CLK1 [get_pins Module_1/clock_1] ...
create_clock -name CLK2 [get_pins Module_2/clock_2] ...

The signals other than the I/Os are called net. The nets may be collected and constrained by using get_nets command, however most of the synthesis tools optimize out them or change the names. It is better to avoid using get_nets if not mandatory. Otherwise most of the synthesis tools require dont_touch attribute or something similar to keep the net.

Normally I don't use get_registers command, because it's not supported by Synopsys Design Compiler, I use get_cells instead. On the contrary, Quartus II supports get_registers according to Altera's SDC manual.

It can be also used to constrain the clock. The manual has the following example:

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
  [get_registers clkdiv]

Alternatively you may use get_pins command. It's up to you.

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
  [get_pins clkdiv/Q]

If you have such a clock divider in your design, it's better to constrain it on the register or Q pin than the clock input of a subblock (e.g. Module_1). Otherwise the synthesis tool doesn't know whether the path carries a clock signal between the register and the clock_1 pin. The delay of the path is not included in the timing analysis etc.

Synthesis tools commonly add suffixes to the signal and cell names. Each tool has its own naming rules. For example, my tool adds _reg suffix to the flopped signals.

Best Answer

Related Solutions

Electronic – Problem getting VHDL syntax correct

Electronic – Get_ports vs Get_pins vs Get_nets vs Get_registers

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