Electronic – VHDL UART core transmitter bits

digital-logicfpgauartvhdl

I was studying the VHDL uart core given here. At the bottom of the page is shown the transmitter code. Notice the line

 tx_data <= "1"&data_i&"01";

This line adds the start and the stop bit to the data string. But why is there an additional '1' bit at the rightmost of the string? Wouldn't the code below suffice? 

 tx_data <= "1"&data_i&"0";

There is no parity implemented in the core, and only 1 bit stop. Thus, that additional bit really confuses me. Why is it there?

Best Answer

The design is hard-coded to send 11 bits per byte. tx_ctr_bit runs from "0000" through "1010", inclusive. So it's obvious that the designer wanted two stop bits per byte.

It is, however, a bizarre choice to send the extra stop bit at the beginning of the byte rather that at the end (i.e., tx_data <= "11"&data_i&"0";). All that does is to increase the latency of the transmitter — when the system wants to send a byte, the start bit comes out one bit time later than it otherwise could.

Another odd thing is the initialization value for tx_data:

  if reset='1' then
    tx_data <= "10111111111";

Why is the 0 bit in there? It doesn't really matter, because this data is never used anyway (except for the LSB, which sets the idle state of the output), but why not just set it to all ones?

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