Electronic – View more than 100 worst-case paths in Quartus II

intel-fpgaquartus-iiverilog

I am using Quartus II to compile Verilog for my FPGA project. For debug, I use SignalTap, which introduces a lot of timing warnings. When I go to the TimeQuest report, and look at the worst-case timing paths, the top 100 slowest paths are related to SignalTap. All the "real" paths are below those 100 SignalTap paths.

How can I view more than 100 worst-case paths in Quartus II?

Best Answer

Go to TimeQuest, generate required reports (I like using Report all summaries macro), select failing report, select failing path clock, right-click -> Report Timing..., Report number of paths: enter a value You like.

It's kind of strange that You get failing paths there TBH...