A flip-flop can only change state when there is a zero-to-one transition in the incoming clock. If J=1 and K=1, Q output will toggle at half the frequency of the CLK.
It may help you (or confuse you) to know that internally a flip-flop can be formed by cascading two level-sensitive latches, the first of which is low-level latching and the second one is high-level latching. When the same clock is fed to both latch enables, the first latch will settle its state when the clock signal (its latch enable) is low. The second latch will settle its state when the clock signal (its latch enable) is high. Note that the input of the second latch is the output of the first latch. The end result is an edge-sensitive device.
The inversion of input is because the NAND inputs are active (forcing the output) when low, and NOR inputs are active (forcing the output) when high. The current state is needed in the truth table as the next state may depend on both the current state and the inputs.
If you look at both outputs of an SR-latch, an active Set will override the output value of the gate Set is connected to. The same applies to reset, e.g. an active Reset will override the output value of the gate it is connected to. If you put both Set and Reset in the 'illegal' condition where both are active, you force both outputs to "00" for a NOR latch and to "11" for a NAND latch.
If both input signals start from the 'illegal' condition (both S and R active) you can create an arbiter circuit. When one of the inputs now goes inactive, the SR latch will remember which input was first to go inactive, for as long as the first input stays inactive. That can for instance be useful to arbitrate between multiple circuits utilizing a bus in an asynchronous design.
However for digital, sequential design the normal use of the SR-latch is to remember one of two previous and volatile states (not three as in the arbiter), thus you need to be careful about not setting both Set and Reset active at the same time, as then your final output will be determined by which of the inputs go inactive first. E.g. if both Set and Reset go inactive at the same clock edge, you have very little control over what state you end up in.
For nearly simultaneous transitions on both Set and Reset (for the SR transitions "10"=>"01", "01"=>"10", and "11"=>"00") you may enter a meta-stable state, where for a duration the output is neither '0' nor '1'. This pretty much means that you cannot determine how it will affect the gate(s) it is driving. Given enough time the metastable state will correct itself due to noise, but you don't know to which value. (In an arbiter you might not care about which way it goes, however you should design to keep a possible metastability event short&small enough to avoid producing an "acknowledge" that you end up retracting. This may not be possible unless you are doing a full custom design, and can be hard even then.).
Best Answer
It depends on how short the pulse is.
If it is extremely short, the transmission gate or tristate element which grants access to the master latch will not have time to even properly turn on, so the bitcell will retain its original value and nothing will happen.
The other case of failure due to minimum pulse width is the case in which the forward element does have time to turn on. But instead, the feedback loop in the bitcell does not have time to settle, and will become metastable. So in this case the output will go to a random value after an indeterminate amount of time.
A third situation; though not necessarily of failure, is when the pulse is long enough to complete the feedback loop, and long enough for the feedback loop to nearly settle. However due to the input getting cut off towards the end, there will be a greater clk->out delay; as it will take longer to settle than with a longer clock pulse. This is not necessarily a failure unless the next stage of logic does not have enough slack to make up for the extra delay.