I'm trying to simulate a voltage dependent current source in LTSpice and I need to have a limited output current. Here is the directive that I am using:
IOUT = LIMIT( K1 * V(1,0), 0.001, -0.001)
In my schematic, IOUT is a regular current source. In this case the current source has a transconductance equal to K1, and samples the voltage across nodes 1 and 0. (And limits the output current to 1mA.)
The weird thing is that my LTSpice directive works fine without the "V(1,0)"
IOUT = LIMIT( K1, 0.001, -0.001)
So does LTSpice not support the V() function or something? How am I supposed to simulate a voltage dependent current source with a limited output current?
Best Answer
Just use the G circuit element (voltage controlled current source) with a lookup table (LUT) specification:
Note: the capacitor C1 is there only to avoid an error because the simulator doesn't like node C to be floating.
This is the relevant section of the online help (emphasis mine):
Here are the results of the simulation:
As you can see you only need to specify two points in the LUT if you just want a VCCS with an hard limiting characteristics, i.e. linear inside a given voltage range and fixed saturated limit out of that range.