The use of a MOSFET for reverse voltage protection is very straight forward.
Some of your references are correct but of low relevance and are tending to make the problem look more complex than it is. The key requirements (which you have essentially already identified) are
MOSFET must have enough Vds_max rating for maximum voltage applied
MOSFET Ids_max rating more than ample
Rdson as low as sensibly possible.
Vgs_max not exceeded in final circuit.
Power dissipation as installed able to sensibly handle operating power of I_operating^2 x Rdson_actual
Power dissipation as installed able to handle turn on and off higher dissipation regions.
Gate driven to cutoff "rapidly enough" in real world circuit.
(Worst case - apply Vin correctly and then reverse Vin instantaneously. Is cutoff quick enough?)
In practice this is easily achieved in most cases.
Vin has little effect on operating dissipation.
Rdson needs to be rated for worst case liable to be experienced in practice. About 2 x headlined Rdson is usually safe OR examine data sheets carefully. Use worst case ratings - DO NOT use typical ratings.
Turn on may be slow if desired but note that dissipation needs to be allowed for.
Turn off under reverse polarity must be rapid to allow for sudden application of protection.
What is Iin max ?
You don't say what I_in_max is and this makes quite a difference in practice.
You cited:
"If the drain-to-source voltage is zero, the drain current also becomes zero regardless of gate–to-source voltage. This region is at the left side of the VGS– VGS(th)= VDS boundary line (VGS – VGS(th) > VDS > 0).
and
Even if the drain current is very large, in this region the power dissipation is maintained by minimizing VDS(on)."
Note that these are relatively independent thoughts by the writer. The first is essentially irrelevant to this application.
The second simply says that a low Rdson FET is a good idea.
You said:
Does this configuration fall under the VDS = 0 classification? That seems like a somewhat dangerous assumption to make in a noisy environment (this will be operating in the vicinity of various types of motors), as any voltage offsets between input supply ground and local ground could cause current to flow. Even with that possibility, I'm not sure I need to spec for my maximum load current on the drain current ID. It would then follow that I don't need to dissipate very much power either. I suppose I could mitigate the problem by Zener clamping VGS closer to VGS(th) to reduce drain current/voltage?
Too much thinking :-).
When Vin is OK get FET turned on asap.
Now Vds is as low as it is going to get and is set by Ids^2 x Rdson
Ids = your circuit current.
At 25C ambient Rds will start at value cited at 25C in spec sheet and will rise if/as FET heats. In most cases FET will not heat vastly.
eg 1 20 milliOhm FET at 1 amp gives 20 mW heating. Temperature rise is very low in any sensible pkg with minimal heatsinking. At 10A the dissipation = 10^2 x 0.020 = 2 Watts. This will need a DPAk or TO220 or SOT89 or better pkg and sensible heatsinking. Die temperature may be in 50-100C range and Rdson will increase over nominal 25C value. Worst case you may get say 40 milliOhm and 4 Watts. That is still easy enough to design for.
Added: Using the 6A max you subsequently provided.
PFet = I^2.R. R = P/i^2.
For 1 Watt disspation max you want Rdson = P/i^2 = 1/36 ~= 25 milliohm.
Very easily achieved.
At 10 milliohm P = I^2.R = 36 x 0.01 = 0.36W.
At 360 mW a TO220 will be warm but not hot with no heatsink but good airflow. A trace of flag heatsink will keep it happy.
The following are all under $1.40/1 & in stock at Digikey.
LFPACK 60V 90A 6.4 milliohm !!!!!!!!!!!
TO252 70V 90A 8 milliohm
TO220 60V 50A 8.1 milliohm
You said:
I suppose I could mitigate the problem by Zener clamping VGS closer to VGS(th) to reduce drain current/voltage?
No!
Best saved for last :-).
This is the exact opposite of what is required.
Your protector needs to have minimal impact on the controlled circuit.
The above has mjaximum impact and increases dissipation in protector over what can be achieved by using a sensibly low Rdson FET and turning it on hard.
You've got that FET drawn backwards, and most of the time gate protection like this is done with a zener diode.
You should make the 9k on your drawing into a 15K , and the 15k resistor into a 15V zener (assuming that 15V is enough to fully enhance the gate of your particular MOSFET). If your MOSFET needs 20V to fully enhance it, then use a 20V zener)
Best Answer
The Zener is better for two reasons:-
The Gate is clamped to a safe voltage no matter what the input voltage, whereas with a resistor divider Gate voltage continues to increase as input voltage increases.
The Zener doesn't reduce Gate voltage when below its Zener voltage, so the FET will still be well turned on at low input voltages.
With resistors you need to balance the required Gate turn-on voltage against the voltage reduction required for protection. That limits the range of input voltages that the circuit can handle, and requires carefully chosen resistor values.
With a Zener, the resistor value just has to be high enough to not overheat the Zener or resistor, but low enough to provide adequate Zener bias current and to discharge the Gate rapidly if the supply voltage is suddenly reversed (so 10K is OK, but 10M might not be).
The 1N4740A is rated for 25mA nominal, but should work down to a bit less than 1mA. At 30V in the resistor has to drop 20V, so its value could range from at least 20V/25mA = 800Ω to 20V/1mA = 20k. At 10V in the FET will get almost the whole 10V so it will still be fully turned on.
With a resistor divider, to get 10V on the Gate one resistor has to drop 20V and the other 10V, thus dividing the input voltage by 3. The lower resistor then has to be twice the value of the upper one, ie. if R1 is 10k then (the resistor in place of) D1 must be 5k.
However at 10V the resistors will still divide the voltage by 3 so the FET will only get 3.3V - not enough to turn it on properly. This could be bad news if the power supply 'browns out' or the load draws a high surge current that momentarily drops the input voltage, as the partially turned on FET could dissipate high power and blow up.