Electronic – What are some things that can be done in VHDL but not in verilog and vice versa

hdlverilogvhdl

VHDL and Verilog are quite similar but do not have the same features, there is certainly a massive overlap though.

What are some things which are easier to do in VHDL but not so easy or even impossible to do in Verilog? I just want to understand how they compare.

I just wonder that if one is as good as the other then why not just use one of the two and simplify the job of the EDA vendors that create tools to simulate and synthesize these HDLs and also the job and life of many other people?

Best Answer

VHDL borrows from Ada, and its strongly typed compared to Verilog. Simple things are easier to do in Verilog, but complex things are easier to do in VHDL. Both can get the job done. Verilog does let you use the C preprocessor which is nice sometimes compared to generics.

Nothing is impossible in either.

Related Solutions

Electronic – How is ASIC design different from FPGA HDL synthesis

Typically ASIC design is a team endeavor due to the complexity and quantity of work. I'll give a rough order of steps, though some steps can be completed in parallel or out of order. I will list tools that I have used for each task, but it will not be encyclopedic.

Build a cell library. (Alternatively, most processes have gate libraries that are commercially available. I would recommend this unless you know you need something that is not available.) This involves designing multiple drive strength gates for as many logic functions as needed, designing pad drivers/receivers, and any macros such as an array multiplier or memory. Once the schematic for each cell is designed and verified, the physical layout must be designed. I have used Cadence Virtuoso for this process, along with analog circuit simulators such as Spectre and HSPICE.
Characterize the cell library. (If you have a third party gate library, this is usually done for you.) Each cell in your library must be simulated to generate timing tables for Static Timing Analysis (STA). This involves taking the finished cell, extracting the layout parasitics using Assura, Diva, or Calibre, and simulating the circuit under varying input conditions and output loads. This builds a timing model for each gate that is compatible with your STA package. The timing models are usually in the Liberty file format. I have used Silicon Smart and Liberty-NCX to simulate all needed conditions. Keep in mind that you will probably need timing models at "worst case", "nominal", and "best case" for most software to work properly.
Synthesize your design. I don't have experience with high level compilers, but at the end of the day the compiler or compiler chain must take your high level design and generate a gate-level netlist. The synthesis result is the first peek you get at theoretical system performance, and where drive strength issues are first addressed. I have used Design Compiler for RTL code.
Place and Route your design. This takes the gate-level netlist from the synthesizer and turns it into a physical design. Ideally this generates a pad-to-pad layout that is ready for fabrication. It is really easy to set your P&R software to automatically make thousands of DRC errors, so not all fun and games in this step either. Most software will manage drive strength issues and generate clock trees as directed. Some software packages include Astro, IC Compiler, Silicon Encounter, and Silicon Ensemble. The end result from place and route is the final netlist, the final layout, and the extracted layout parasitics.
Post-Layout Static Timing Analysis. The goal here is to verify that your design meets your timing specification, and doesn't have any setup, hold, or gating issues. If your design requirements are tight, you may end up spending a lot of time here fixing errors and updating the fixes in your P&R tool. The final STA tool we used was PrimeTime.
Physical verification of the Layout. Once a layout has been generated by the P&R tool, you need to verify that the design meets the process design rules (Design Rule Check / DRC) and that the layout matches the schematic (Layout versus Schematic / LVS). These steps should be followed to ensure that the layout is wired correctly and is manufacturable. Again, some physical verification tools are Assura, Diva, or Calibre.
Simulation of the final design. Depending on complexity, you may be able to do a transistor-level simulation using Spectre or HSPICE, a "fast spice" simulation using HSIM, or a completely digital simulation using ModelSim or VCS. You should be able to generate a simulation with realistic delays with the help of your STA or P&R tool.

Starting with an existing gate library is a huge time saver, as well as using any macros that benefit your design, such as memory, a microcontroller, or alternative processing blocks. Managing design complexity is a big part as well - a single clock design will be easier to verify than circuit with multiple clock domains.

Electronic – How to design processors / microprocessor [ not broad ]

If you let the tools do the designing portion of your processor (or microprocessor), then wont it always infer the same circuit, or at least nearly same circuit for your processor ?

No. There are several low-level details which will result in different circuitry. Suppose you design an adder. You are really only designing the functional specification of the adder, either in high level terms (e.g. verilog "+" operator) or lower level terms such as gates. However this design must be mapped onto the actual blocks or gates which will implement the design. On an FPGA you may have a macro-cell or a look-up table (LUT) structure which gets repeated in an array across the chip. For an ASIC you have raw gates.

As part of this there is typically some kind of "place and route" step which will map the functional blocks onto the two dimensional layout of the resources on the FPGA or ASIC. Placing an routing are not simple algorithms - my understanding is that they are "NP complete" as there is not a polynomial time algorithm to find the optimum layout and routing. As a typical part of a design you will specify timing constraints to be met, and the place and route will try to operate so that these constraints are met. Because the process is not exhaustive (it would take too much time) a "seed" value is typically used to determine how to start out, and then a solution is looked for that is close to where it needs to be. Different seeds will produce different layouts with the same functional characteristics but (usually slightly) different timings.

If I am correct above ( which obviously I doubt ), then how would the designs differ ? In other words, where lies the role of a human / engineer if everything is done by the tools .

As other answers have mentioned, the actual functional design is not done by the tools. But there is still room for human interaction with the tools in determining the actual functioning. In addition to specifying timing requirements it is sometimes necessary to go back and tweak the design to accomodate these requirements. For instance, the tools might identify a critical path which limits the clock frequency at which the design can run. This might be slower than is desired, and the engineering would need to go back and figure out how to make it meet timing, such as pipelining, reducing fan-out, and so forth.

Best Answer

Related Solutions

Electronic – How is ASIC design different from FPGA HDL synthesis

Electronic – How to design processors / microprocessor [ not broad ]

Related Topic