Electronic – What are the jitter characteristics of PLLs internal to Stratix V FPGAs

Its a term used to try to bridge the world from ASIC & discrete logic to how FPGA function with their slices and lookup tables. One slice could be used to create a single AND gate or a to some extent part of a larger adder. By rationalising the equivalent logical gates required is some pseudo way of marketing their size.

See page 141 of "Section 3" available here for jitter requirements for 1000BASE-SX and 1000BASE-LX Ethernet.