Electronic – What are the NAND Trees that Ethernet datasheets refer to

ethernet

I have read a few Ethernet transceiver datasheets and they always have some short section akin to "NAND Tree Support" or "NAND Tree I/O Testing", and from what I gather from these small bits of information is that they offer some standardized facility for hardware fault detection.

In general, they describe how to enable NAND Tree mode, what pins are probed, what order they are probed in, and how to read the results of the test. But none of the datasheets I have read to date have provided an in-depth description of how these tests actually operate.

Can anyone shed some light on this for me?

Best Answer

Here is a link to a TI document that describes a NAND tree test.

Basically, the chip connects all the pins to a series of NAND gates. Driving all of the inputs low drives the output high. Now, you drive the inputs individually high. If the pin's internal connections are good, the output will go low.

This lets you test all of the pins using just one output.